Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders

Abstract

In this study, two asynchronous delay insensitive adder topologies in null convention logic (Fant and Brandt, 1997) style are adopted for bit-level pipelining: The reduced null convention logic adder (Smith, 2001) and a null convention carry save adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry generation, with O(log n) average completion time for n-bit addition and -as a result of bit-level pipelining- constant throughput against increased bit-length.