Drain Doping Concentration Research Articles

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

DC and RF/analog parameters in Ge‐source split drain‐ZHP‐TFET: Drain and pocket engineering technique

AbstractIn this article, a Ge‐source is employed in split drain Z‐shaped line TFET structure (SD‐ZHP‐TFET) and named as Ge‐source SD‐ZHP‐TFET. The presence of split drain increases the tunnel width at interface of channel–drain, which reduces the ambipolar current (IAMB). Also, the horizontal pocket at source region and the Ge‐source boost the ON current (ION) of the SD‐ZHP‐TFET. A comparative study in terms of transfer characteristic, current ratio (ION/IOFF and ION/IAMB), transconductance (gm), and cut off frequency (fc) among ZHP, SD‐ZHP, and Ge‐source SD‐ZHP TFETs are highlighted through TCAD simulator. We have reported DC and RF/analog figure of merits (FoM) for the variation in thickness of horizontal pocket (thp) and doping concentration (Nhp) in the horizontal pocket region by plotting transfer characteristic, gm, and fc for Ge‐source SD‐ZHP‐TFET. Furthermore, the impact of drain doping concentration of region 1 (Ndu) and region 2 (Ndl) on transfer characteristic, IOFF, IAMB, gm, Cgg, and fc are studied in proposed TFET. The Ge‐source SD‐ZHP‐TFET provides ION/IOFF and ION/IAMB in the order of 109 and 1011, respectively. Moreover, Ge‐source SD‐ZHP‐TFET has maximum gm and maximum fc at higher value of thp, Nhp, Ndu, and Ndl. It is also seen that the proposed device shows an improved RF/analog and DC characteristic even with scaling down of gate bias (VG). Finally, the various parameters of Ge‐source SD‐ZHP‐TFET is compared with the data exist in the literature.

Analytical Modeling of Line-Tunneling TFETs Based on Low-Bandgap Semiconductors

The combination of two techniques: low-bandgap semiconductor and line-tunneling structure is an effective way to achieve the highest on-current in TFETs. In this paper, design of low-bandgap line-tunneling TEFT and its analytical modeling of drain current equation is proposed. The previously suggested drain current equation for the low-bandgap line-tunneling TEFT has been explained in a relatively complex form based on the minimum tunnel path that is an effective factor in determining band-to-band tunneling (BTBT). It has been simplified in this paper and reformulated based on gate-to-source voltage. Important design factors such as source doping concentration, material and thickness of the gate-insulator were examined by simulation and numerical calculations based on the minimum tunnel path for two low-bandgap In0.88Ga0.12As and relatively high-bandgap GaSb semiconductors. The comparison of the results obtained from simulations with the proposed analytical drain current model show a good agreement. Drain doping concentration, is an effective factor on the off-state current of low-bandgap TFET. This factor was examined in order to reduce the off-current.

Analytical and Compact Modeling Analysis of a SiGe Hetero-Material Vertical L-Shaped TFET

This paper deals with the development of a novel 2-D analytical modeling of heterojunction vertical L-shaped tunnel FET for characterisation of surface potential and drain current. The compact analysis includes the properties of dual modulation effect with the numerous efforts to predict the characteristics of current and to discuss the method of device improvement. The dual modulation effect is used to regulate the biasing voltage at both the junction of source and drain of surface potential to determine the tunneling width. A 2-D Poisson equation is solved for the proposed model by using parabolic approximation method with constant electric field which are used to determine the effect of SiGe mole-fraction, gate-drain biasing potential, dielectric constant of gate oxide, drain doping concentration, metal gate work-function and different binary compound material on the device surface potential. Most importantly, a new channel surface potential expression is derived that can forecast the effect of drain and gate biasing. The derived model results are compared with those of simulated results in order to evaluate the validity of electrical parameter model.

Performance Analysis of Group IV Material Based Tunnel Field Effect Transistor: Effect of Drain Splitting and Introducing Ge-Strip at Source- Channel Junction

The performance effect of splitting and abrupt doping in the drain region, use of a Ge strip at source-channel junction in group IV material based (Ge1 − xSnx/ Si1 − y − zGeySnz) Tunnel Field Effect Transistor (TFET) is investigated in the present manuscript. The variation of certain device parameters, such as mole fraction, different gate dielectrics, gate dielectric thickness and drain doping concentrations are applied to analyze the performance of proposed group IV material based TFET in terms of current-voltage (I-V) characteristics, potential profile and ION/IOFF ratio using device simulator SILVACO TCAD. The simulation results obtained for the proposed TFET structure are compared with the other TFET structures available in the literature, which shows better results as ION/IOFF ratio was received of the order of 1012 in comparison to conventional group IV material based TFET and subthreshold swing of 25.03 mV/decade, which makes the proposed structure promising for high speed switching action with low power CMOS compatibility.

Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.

Monte Carlo Study of Si, Ge, and In&lt;sub&gt;0.53&lt;/sub&gt;Ga&lt;sub&gt;0.47&lt;/sub&gt;As n-Channel FinFET Scaling: Channel Orientation, Quantum Confinement, Doping, and Contacts

The effects of channel scaling in silicon (Si) and Si-alternative germanium (Ge) and In0.53Ga0.47As (InGaAs) n-channel devices toward the end of the CMOS roadmap are addressed theoretically. The devices are simulated using a quantum-corrected semiclassical Monte Carlo method. The results are discussed with an emphasis on the underlying physics. Multiple effects of quantum conf inement within the channel, far-from equilibrium-degenerate statistics, saddle/slot contact geometries with appropriate material-dependent specific contact resistivities, and appropriate material-dependent source and drain doping concentrations are considered, with the exception of the contact resistivity of Ge, which is idealized to reflect what may be possible if the currently prohibitive contact challenge can be overcome.

Study of parametric variations on hetero-junction vertical t-shape TFET for suppressing ambipolar conduction

This paper investigates a hetero-junction vertical t-shape tunnel field effect transistor and discussed various methods for the suppression of ambipolar conduction for the first-time utilizing computer aided design sentaurus simulation tool. This device is primarily consisting of dual gate silicon based gated p-i-n diode for eminent control over the channel. Further, introduction to the 10 nm silicon germanium layer to the channel makes aggressive improvement to the device characteristics. Unlike to the conventional TFET, we have considered the effective techniques like gate-on-drain overlapping, gate-on-channel underlapping and different drain doping concentration up to 1 × 1018 cm−3, which are used to conquer the ambipolar conduction by increasing the tunneling barrier width at the drain channel edges. The device surface potential performance is also analyzed for different parameters like drain doping concentration, gate-source voltage, silicon germanium Si1-xGex mole fraction x and gate oxide thickness. Moreover, the vertical and lateral electric field inspect for determining the tunneling rate. The path distribution of source channel and drain in vertical direction will increase the scalability of the simulated device.

Influence of the Biomaterial Thickness in a Dielectrically Charged Modulated Fringing Field Bio-Tunnel-FET Device

The biosensor market is expected to increase more than 40% in 5 years ( 2019 to 2024) due to the versatile of these devices (1). Many research groups are studying new types and optimizations of these devices and the tunnel field-effect transistors (TFET) have attracted the interest due to the many advantages of these devices (2).Figure 1 shows the Bio-TFET cross section which has been simulated with TCAD Sentaurus (3). The proposed device has a gate length (LG), equivalent gate oxide thickness (tox) and channel silicon thickness (tSi) of 40 nm, 1 nm and 10 nm. The drain underlap (LUD) is variable in the range of 1 to 100 nm. The uniform doping profile of the device consists of a source and drain doping concentration of 1020 atom/cm3 of boron and arsenic, respectively. An intrinsic channel with 1015 atom/cm3 of boron. The gate electrode has a workfunction of 4.7 eV. The main models incorporated in the simulation were the bandgap narrowing (BGN), Shockley Read Hall recombination (SRH) and the nonlocal band-to-band tunneling (BTBT). In the drain underlap region is deposited a biomaterial for biosensing purposes. This material has a dielectric constant (k, where ε=k*ε0) of 1 (air), 2.1 (Streptavidin), 3.57 (APTES), 8 (Anti-Iris antibody) and 10 (Isoquinoline) (4).Figure 2 shows the Bio-TFET transfer characteristics. The ambipolar region is a parasitic tunneling current that occurs for negative gate bias (VG) for nTFET at drain to channel region. In order to decrease this effect a drain underlap (LUD) is performed at the device (5). However, when the biomaterial dielectric constant (k) increases, the ambipolar current also increases orders of magnitude, meaning that the device is very susceptible to k variation in the biomaterial region and can be used for biosensing of different types of biomolecules with a distinct k. In order to quantify the influence of change in k in the biomaterial region the equation in terms of ID: Sensitivity = ΔID/ID(Ref.) was used. Where ΔID represents the difference between the drain current of biosensing (output), e.g., the drain current with the presence of biomaterial ID(Bio) and the drain current of reference ID (Ref.) (input), e.g., drain current without biomaterial ID (k=1) . Both for a fixed value of gate voltage (VG = -2 V) in the ambipolar region. Fig.3 shows the sensitivity of the device as a function of LUD for different k values. The maximum sensitivity occurs for a LUD = 30 nm for all range of k values. The sensitivity increases for higher k as reported in (6). Another parameter that is important for sensing is the dimension of the target. Many biomolecules have different types, e.g., spherical, ellipsoidal or elongated (7). Therefore, the study of the parameter is fundamental for the functional operation of the device. In Fig.4 the sensitivity is analyzed as a function of biomaterial thickness (tBio) for a fixed value of LUD=30nm. With the rising of tBio and k the sensitivity increases, i.e., exceeding 2 orders of magnitude comparing tBio = 10nm and tBio = 30 nm for k = 10. This increment on sensitivity is due to the tunneling length lowering, as can be noticed in Fig.5. The tunneling length decrease from 5.7 nm (tBio= 10 nm) to 9.5 nm (tBio = 30 nm), both for k = 10 and fixed energy of - 1 eV. The lowering of the tunneling length increases the ambipolar current ID(Bio) that enhances the sensitivity of the device. An important consideration for the biosensing process is the charge on the biomaterial that affect the tunneling current and therefore affect the sensitivity of the device. In Fig. 6, the sensitivity is studied as in the function of positive fixed charges in the range of 1010 to 1012 cm-2. The sensitivity increases for thicker values of tBio. This is due to the higher effect of the fringing field in the region. As tBio increase the effect of fringing field increases in the biomaterial region and as consequence, the device becomes more sensible with the presence of charges.The study of charges and biomaterial thickness in a dielectrically modulated fringing field Bio-TFET was performed in this work. The device shows high sensitivity with the increase of tBio in the range studied in this work. Although, the effect of fixed charges is more notable for thicker tBio. Then, the tBio thickness shows a high impact in the sensing of the device. Figure 1

Optimization of Electrical Parameters of Pocket Doped SOI TFET with L Shaped Gate

In this work, a pocket doped hetero source Silicon-on-insulator Tunneling Field Effect Transistor (SOI-TFET) with L shaped gate including back gate is proposed. The operation of this device is primarily dependent on band to band tunneling. Performance of a p-i-n TFET (proposed structure 1) is examined against the SOI double gate TFET (proposed structure 2). A brief investigation of the proposed device has been done by drain bias variation, EOT scaling, channel length modulation, pocket thickness variation, substrate dimension scaling and back gate voltage variation using Sentaurus TCAD software. The device performance is optimized for different source, drain, channel and pocket doping concentration and work function tuning of the front gate. It provides a high Ion/Ioff ratio, best reported 3.326 × 1011; steep Subthreshold Swing, SS best reported point SS 22.21 mV/decade (2 nm gate oxide) and average SS 31.74 mV/decade (3 nm gate oxide). The ON current is found to be high i.e. in the orders of mA. The proposed device is immune to short channel effects like DIBL and channel length modulation.

A Full-Range Analytical Current Model for Heterojunction TFET With Dual Material Gate

In this brief, based on the Gaussian quadrature method, we develop an analytical drain current model for the dual-material-gate heterojunction tunnel field-effect transistor (DMG-H-TFET) due to its advantages over the H-TFET and DMG-TFET. This model accounts for the effects of source depletion, drain depletion, ambipolar behavior, and mobile charge both in inversion and accumulation states. The accuracy of the model is validated against TCAD simulation and published data. The dependences of the surface potential, electric field, and drain current on biases and drain doping concentrations are well predicted. Besides, in comparison with the conventional H-TFET, the improvement in drain current and the alleviation of delayed saturation in DMG-H-TFET can also be observed through the proposed model.

Study on Random Dopant Fluctuation in Core–Shell Tunneling Field-Effect Transistors

Random dopant fluctuations (RDF) of conventional and core–shell tunneling field-effect transistors (TFETs) are investigated using 3-D numerical simulations. Sano model was adopted to consider short- and long-range Coulomb potentials separately under drift-diffusion transport. Core–shell TFETs have much smaller average subthreshold swing and greater on-state performance than do conventional TFETs. Conventional TFETs have small tunneling area which is the source/channel interface near the gate, so the device-to-device performance variations are significant. Core–shell TFETs, on the other hand, have wide tunneling area which is the core–shell interface, thus averaging out the performance variations induced by the RDF effects. Longer drain-side extension lengths decrease the ambipolar effects without increasing channel resistance, but changing drain-side extension lengths or/and drain doping concentrations of the conventional TFETs does not reduce the performance variations. Overall, the core–shell TFETs have the variations of threshold voltages and on-state currents which are 34% and 68% smaller than those of the conventional TFETs, respectively. Therefore, the core–shell TFETs are advantageous of dc performance as well as of RDF immunity, promising for nanoscale low-power applications.

Effects of annealing gas and drain doping concentration on electrical properties of Ge-source/Si-channel heterojunction tunneling FETs

Improvement in the performance of Ge-source/Si-channel heterojunction tunneling FETs (TFETs) with high on-current/off-current (Ion/Ioff) ratio and steep subthreshold swing (SS) is demonstrated. In this paper, we experimentally examine the effects of gas ambient [N2 and forming gas (4% H2/N2)] and a doping concentration in the drain regions on the electrical characteristics of Ge/Si heterojunction TFETs. The minimum SS (SSmin) of 70.9 mV/dec and the large Ion/Ioff ratio of 1.4 × 107 are realized by postmetallization annealing in forming gas. Also, the steep SSmin and averaged SS (SSavr) values of 64.2 and 78.4 mV/dec, respectively, are obtained in low drain doping concentration. This improvement is attributable to the reduction in interface state density (Dit) in the channel region and to the low leakage current in the drain region.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias (VG) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG. The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Effects of drain doping concentration on switching characteristics of tunnel field-effect transistor inverters

In order to investigate the effects of the modulation of drain doping concentration (Ndrain) on alternating current (AC) switching characteristics of a tunnel filed-effect transistor (TFET) inverter, the characteristics of TFETs with various Ndrains are analyzed rigorously through mixed-mode device and circuit TCAD simulations. As the Ndrain gets decreased, the drain current (ID) becomes reduced and the gate-to-drain capacitance (CGD) reflects the entire gate capacitance (CGG) at a lower gate voltage (VG), which leads to the degradation of falling/rising delay in TFET inverters. These phenomena are explained successfully by the change of quasi-Fermi energy in the drain (EF_drain) as a function of VG. The EF_drain rises dramatically from when tunneling current starts to flow from the source in the n-type TFET with low Ndrain. As a result, drain-side channel inversion occurs at a lower VG due to the reduction of the energy barrier between the EF_drain and the conduction band edge of the channel.

Characteristics of cylindrical surrounding-gate GaAsxSb1−x/InyGa1−yAs heterojunction tunneling field-effect transistors**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176038 and 61474093), the Science and Technology Planning Project of Guangdong Province, China (Grant No. 2015A010103002), and the Technology Development Program of Shaanxi Province, China (Grant No. 2016GY-075).

A III–V heterojunction tunneling field-effect transistor (TFET) can enhance the on-state current effectively, and GaAsx Sb1−x/InyGa1−yAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition. In this paper, the performance of the cylindrical surrounding-gate GaAsx Sb1−x/InyGa1−yAs heterojunction TFET with gate–drain underlap is investigated by numerical simulation. We validate that reducing drain doping concentration and increasing gate–drain underlap could be effective ways to reduce the off-state current and subthreshold swing (SS), while increasing source doping concentration and adjusting the composition of GaAsx Sb1−x/InyGa1−yAs can improve the on-state current. In addition, the resonant TFET based on GaAsx Sb1−x/InyGa1−yAs is also studied, and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current, respectively, and is much superior to the conventional TFET.

Design optimization of vertical nanowire tunneling field-effect transistor based on AlGaSb/InGaAs heterojunction layer

This paper presents the electrical characteristics of vertical nanowire-type tunneling field-effect transistors (VNW TFETs) based on the AlGaSb/InGaAs heterojunction for low-power, high-speed applications. The proposed devices have a very steep junction, based on broken band alignment between the AlGaSb and InGaAs layers. The extremely thin tunneling barrier increases the tunneling probability between the AlGaSb source region and the InGaAs channel region. For this reason, the broken band based on the AlGaSb/InGaAs heterostructure enhances the on-state current (Ion) of the TFETs. To optimize the electrical performance of the proposed device, design optimization using technology computer-aided design (TCAD) simulations is performed. The design variables are gate length, doping concentrations, and the nanowire radius. The optimized device has a gate length of 30 nm, channel and drain doping concentrations of 1018 cm−3, and a radius of 10 nm. Results confirm that the optimized TFET has a subthreshold swing (S) of 27.8 mV/dec and an Ion value of 2.57 mA/μm.

Analysis of Graphene Tunnel Field-Effect Transistors for Analog/RF Applications

The recent findings of quasi-saturation and negative differential resistance in graphene FET have motivated the researchers to improve the current saturation behavior. We suggest that tunnel FET (TFET) with graphene can be a potential candidate for better current saturation. In this regard, the electronic transport in zero bandgap graphene TFET (T-GFET) is studied through the self-consistent solution of Schrödinger equation within ballistic nonequilibrium Green's function formalism, and 2-D Poisson's equation. We show that the appropriate drain overlap, and channel and drain doping concentrations in T-GFET can significantly suppress the channel to drain tunneling current and, consequently, enhance the current saturation. Despite T-GFET's lower ON-current, it shows moderately higher intrinsic gain, compared with conventional graphene FET (C-GFET). Furthermore, the channel length dependence of intrinsic gain and cutoff frequency for T-GFET is investigated and compared with C-GFET.

An accurate closed-expression model for FinFETs parasitic resistance

A new closed-expression analytic model for parasitic resistance of FinFETs (Fin-Field-Effect-Transistors), which allows a fast estimation of this parasitic element, is proposed and evaluated in this work. The parasitic resistance is one of the most significant parameter for performance and reliability degradations in scaled devices. The model is based in the current distribution observed in three-dimensional simulations and is very accurate when compared to experimental data. The contact resistance was modeled using a variable impedance transmission line model, to approximate source and drain geometries to the real shapes of these regions. The model has a closed expression, without adjustment parameters. All results were compared with two previous models presented in literature, and the proposed model was the one which presented the best accuracy: percent errors below 10% for different source and drain doping concentrations, contact lengths, extension lengths, contact resistivity and fin widths.

Influence of contact doping on graphene nanoribbon heterojunction tunneling field effect transistors

We investigated the device performance of graphene nanoribbon tunneling field-effect transistors with heterogeneous channel as a function of the contact doping concentrations. The simulations were carried out based on the non-equilibrium Green’s function, coupled with a Dirac Hamiltonian model, and the roles of symmetric and asymmetric contact doping concentrations on the device performance were identified. It was observed that the device performances such as OFF-state currents (IOFF), ON-state currents (ION) and subthreshold slopes (SSs) were greatly influenced by the source doping concentrations, while variations in drain doping concentrations changed mainly the IOFF. By applying proper asymmetric source and drain doping concentrations, low SS and large ION/IOFF ratio can be achieved, indicating that it is an alternative route to effectively enhance the device performance.