Drain Current Mismatch Research Articles

Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> characteristics show a nonmonotonic “hump” induced by the haloregion/channel-region junction barrier. Another key careabout for analog design - the drain current (ID) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise (1/f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">noise</sub> ) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature.

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K.

Characterization and Modeling of Mismatch in Cryo-CMOS

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

Analysis and Modeling of Current Mismatch in Laterally Nonuniform MOSFETs

We present an analytical modeling approach for drain current ( ${I}_{D}$ ) mismatch in lateral nonuniformly doped (NUD) MOSFETs. The model uses the carrier number fluctuation theory to include the effect of random dopant fluctuations (RDFs) on inversion charge fluctuation (ICF) in different operating regions. Our analysis shows that the conventional models for uniformly doped device underestimate the ${I}_{D}$ mismatch by one-to-two orders of magnitude at low gate voltages in NUD devices. We have also considered the effect of RDF on mobility fluctuation (MF), which shows its significant role in strong inversion (SI). To investigate the physical mechanism leading to such a behavior, extensive technology computer-aided design simulations are performed for various conditions of bias, doping profiles, and temperature. Using the impedance field method to calculate the relative contributions of RDF to ICF and MF, we show that our model can successfully capture the drain current mismatch across subthreshold to SI in the NUD device.

Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs

In this paper, we present a complete study of the drain and gate current local variability in high- ${k}$ /metal gate-stack 14-nm fully depleted silicon-on-insulator CMOS transistors. A thorough experimental characterization of both drain and gate current mismatch was performed. In addition, we developed, for the first time, models of the drain and gate current mismatch, valid in all operation regions. Finally, we demonstrate the universal validity of our models through Monte Carlo simulations.

Forced Current Balancing of Parallel-Connected SiC JFETs During Forward and Reverse Conduction Mode

In this paper, a thorough investigation on the parallel connection of the latest generation vertical trench silicon carbide (SiC) junction field-effect transistors (JFETs) during forward and reverse conduction is performed. Both enhancement and depletion mode SiC JFETs are examined, regarding their static and dynamic characteristics. A parametric analysis on the current sharing, reliability, and effectiveness of the parallel connection is carried out. Current asymmetry over the different JFETs is monitored via series-connected current transformers. A forced current balancing technique during forward conduction mode is achieved by controlling the time delay of the gate signal through a low-cost digital signal controller. The drain current mismatch during reverse conduction is also studied and addressed by applying similar techniques as in the forward conduction, or by adding an antiparallel power diode. The performance of paralleled JFETs is validated through simulation and experimental results at room temperature and 150 °C.

Modeling of Drain Current Mismatch in Organic Thin-Film Transistors

In this paper, we present a consistent model to analyze the drain current mismatch of organic thin-film transistors. The model takes charge fluctuations and edge effects into account, to predict the fluctuations of drain currents. A Poisson distribution for the number of charge carriers is assumed to represent the random distribution of charge carriers in the channel. The edge effects due to geometric variations in fabrication processes are interpreted in terms of the fluctuations of channel length and width. The simulation results are corroborated by experimental results taken from over 80 organic transistors on a flexible plastic substrate.

Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

In this letter, we demonstrate the existence of the source-drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on Y-function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies

In this work the threshold voltage ( V t ), the current gain factor ( β ), and the drain current ( I D ) mismatch trends for 20 nm Gate-Last bulk CMOS technology integrating High- k /metal gate are investigated. The reported results indicate that the high k /metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the V t mismatch and good performance in terms of the β mismatch. This study further demonstrates that the I D variability mainly depends on the mismatch trends of V t and β , and on the contributions of the transconductance divided by the drain current ( G m / I D ) and the source drain series resistance ( R sd ) terms. The 20 nm Gate-Last technology exhibits significant improvement in the V t and β mismatch performance as compared to the 28 nm Gate-First counterpart. The evolution of the V t and β mismatch parameters, iA Δ Vt and iA Δ β / β , is further analyzed as a function of the electrical oxide thickness EOT ( T ox ) along the technology nodes from 90 nm to 20 nm. A clear trend towards a reduction of the y -axis intercept (i.e. offset) of the linear plot of iA Δ Vt as a function of EOT is observed starting at the 28 nm Gate-First technology, with the offset approaching zero for the 20 nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances.

Total dose effects on the matching properties of deep submicron MOS transistors

Based on 0.18 μm MOS transistors, for the first time, the total dose effects on the matching properties of deep submicron MOS transistors are studied. The experimental results show that the total dose radiation magnifies the mismatch among identically designed MOS transistors. In our experiments, as the radiation total dose rises to 200 krad, the threshold voltage and drain current mismatch percentages of NMOS transistors increase from 0.55% and 1.4% before radiation to 17.4% and 13.5% after radiation, respectively. PMOS transistors seem to be resistant to radiation damage. For all the range of radiation total dose, the threshold voltage and drain current mismatch percentages of PMOS transistors keep under 0.5% and 2.72%, respectively.

Mismatch Simulation of Motion Detection Pointing Device

A motion detection pointing device based on CMOS image sensor is presented in this paper. Mismatch of active pixel sensor and correlated double sampling circuit is analyzed by Monte Carlo method using H-SPICE. With a 3.3V supply voltage, the maximal offset voltage caused by all mismatch is 3.6043mV, less than 8-bit least significant bit. Therefore, the motion detection pointing device system could achieve 8bit precision. The contribution of each mismatch to the total maximal offset voltage is also analyzed, comparison shows photo diode current mismatch and saturation drain current mismatch are the main causes of offset voltage. Keywords: mismatch; offset voltage; Monte Carlo method

Mismatch reduction technique for transistors with minimum channel length

An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and ?3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier's anticipated input-referred offset voltage improves to 0.76---1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6---1.0%.

Drain-current variability in 45 nm bulk N-MOSFET with and without pocket-implants

In this work, the drain-current mismatch is characterized from linear to the saturation regime. Characterizations are performed for N-MOS transistors with and without pocket-implants. A general drain-current mismatch model for transistors without pocket-implants, valid for any operation region, is also presented. It has been shown that correlated mobility and threshold voltage fluctuations must be considered to qualitatively model the experimental results. A comparison between devices with and without pocket-implants is performed and an important drain-current mismatch enhancement in the latter case is reported and discussed.

Temperature Dependence of Drain Current Mismatch in Nanoscale Uniaxial-Strained PMOSFETs

This letter reports new findings on the temperature dependence of mismatching properties in nanoscale uniaxial-strained pMOSFETs. Our results reveal that the temperature dependence of drain current mismatch can be modulated by uniaxial strain. In the high gate-voltage overdrive linear region, the compressively strained device shows smaller increment in drain current mismatch than the unstrained counterpart as temperature decreases. In the high saturation region, opposite to the unstrained case, the drain current mismatch of the compressively strained device decreases with temperature. The underlying mechanism is the larger temperature sensitivity of carrier mobility for the strained device.

FinFET Mismatch in Subthreshold Region: Theory and Experiments

In this paper, we study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view. We propose a simple model that takes into account the effect of threshold voltage and subthreshold swing fluctuations and their correlation. For long-channel devices (longer than a critical length LC), characterized by a subthreshold swing close to the ideal value, the overall current mismatch is dominated by threshold voltage fluctuations and, therefore, is gate voltage independent. The subthreshold swing fluctuations give a negligible effect on the drain-current mismatch and are uncorrelated with the threshold voltage fluctuations. For short-channel devices (shorter than a critical length LC), characterized by a strong dependence of subthreshold swing on the channel length, the overall current mismatch presents an additional relevant contribution associated with the subthreshold swing fluctuations. This component depends on the gate voltage overdrive and is ascribed to the gate line edge roughness, resulting in a partial correlation between threshold voltage and subthreshold swing fluctuations.

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

This paper investigates and analyzes the matching properties of nanoscale strained MOSFETs under various bias conditions. Through a comprehensive comparison between coprocessed strained and unstrained PMOSFETs, the impact of process-induced uniaxial strain on the matching performance of MOS devices has been assessed and analyzed. Our examination indicates that, in the low-gate-voltage-overdrive (|V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gst</sub> |) regime, the normalized drain current mismatch (¿(¿I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> )/I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) of the strained device is almost the same as that of the unstrained one at a given transconductance to drain current ratio ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ). In the high |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gst</sub> | linear regime, the ¿(¿I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> )/I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> for the strained device is smaller than that of the unstrained one because of its smaller normalized current factor mismatch. In the high |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gst</sub> | saturation regime, the improvement in the ¿(¿I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> )/I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> for the strained device is further enhanced because of the reduced critical electric field at which the carrier velocity becomes saturated.

A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs

This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub -100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> . This paper may provide insights for analog design using advanced strained devices.

The statistics of NBTI-induced V/sub T/ and β mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.

Matching behaviours of analogue NMOSFET parameters under hot-carrier stress

In this paper, we provide some experimental results of NMOSFET hot-carrier degradation for analogue circuit application. After hot-carrier stress, over the whole range of gate voltages, the drain current mismatch and output conductance are measured in the saturation region. Evidence of hole and electron trapping is found near the drain under low and high biased gate voltages, respectively, which is believed to be the cause of the variation of the output conductance during stress. Under low-gate-voltage stress, acceptor-like interface traps are also generated and compensate for the influence of trapped holes.