Drain Current Instability Research Articles

Drain Current Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors with Different Active Layer Thicknesses.

In this study, the initial electrical properties, positive gate bias stress (PBS), and drain current stress (DCS)-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with various active layer thicknesses (TIGZO) are investigated. As the TIGZO increased, the turn-on voltage (Von) decreased, while the subthreshold swing slightly increased. Furthermore, the mobility of over 13 cm2·V−1·s−1 and the negligible hysteresis of ~0.5 V are obtained in all of the a-IGZO TFTs, regardless of the TIGZO. The PBS results exhibit that the Von shift is aggravated as the TIGZO decreases. In addition, the DCS-induced instability in the a-IGZO TFTs with various TIGZO values is revealed using current–voltage and capacitance–voltage (C–V) measurements. An anomalous hump phenomenon is only observed in the off state of the gate-to-source (Cgs) curve for all of the a-IGZO TFTs. This is due to the impact ionization that occurs near the drain side of the channel and the generated holes that flow towards the source side along the back-channel interface under the lateral electric field, which cause a lowered potential barrier near the source side. As the TIGZO value increased, the hump in the off state of the Cgs curve was gradually weakened.

Reliability of Highly Stable Amorphous-Silicon Thin-Film Transistors Under Low Gate-Field Stress—Part II: Optimization of Fabrication Conditions and Gate Voltage Dependence

Part I of this paper introduced a two-stage model for reliability characterization and lifetime prediction of amorphous-silicon thin-film transistors (a-Si TFTs) under low gate-field stress that includes both charge trapping in the silicon nitride (SiNx) gate dielectric and defect generation in the a-Si channel. In part II, the model is used to experimentally reduce the drain current instability under room temperature operation of a-Si TFTs under a prolonged gate bias of 5 V. Deposition conditions for the SiNx gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive-ion-etch steps, or with all wet-etch steps. The stability of the a-Si channel also depends on the deposition conditions for the underlying SiNx gate insulator, and TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% lifetime of the drain current of back-channel-passivated dry-etched TFTs under continuous operation in saturation at 20 °C with $V_{\mathrm{GS}}=\text{5} \text{V}$ from $\text{3}\times \text{10}^{4} \text{s}$ (9.2 h) to $\text{4}\times \text{10}^{7} \text{s}$ (1.4 years). We also extend the model, so that parameters from the degradation at one gate voltage can be used to estimate the degradation at other low gate voltages.

Phenomenon of Drain Current Instability on p-GaN Gate AlGaN/GaN HEMTs

In this paper, an observation of drain current instability on p-GaN gate AlGaN/GaN HEMTs is reported. Contrary to the Schottky gate AlGaN/GaN HEMTs, which show stable and consistent I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> curves under different pulsed conditions, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> curves for p-GaN gate AlGaN/GaN HEMTs show a dispersion in the saturation region under the same pulse conditions, which cannot be explained by the trapping of electrons in the material. A model considering the trapping of holes in the p-GaN gate under different gate and drain biases is proposed to explain this new phenomenon.

Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

Negative bias-temperature (NBT) stress-induced drain current instability in a pMOSFET with a gate stack is investigated by using a fast transient measurement technique. We find that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent poststress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Poststress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model. The impact of NBT stress voltage, temperature, and time on drain current instability mode is evaluated.

Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs

In this work, the instability of n-channel 4H–SiC double-implanted metal–oxide–semiconductor field-effect-transistors (DMOSFETs) was studied, in terms of threshold-voltage ( V TH) shifts and drain–source current ( I DS) transients, for different gate bias stress durations of range 100–5500 s. At room temperature, for positive gate bias stress, the V TH shift and I DS decay increase with increasing stress time. The V TH shift and the I DS decay were recovered by negative gate bias stress. It is believed that the instability in device behavior during positive gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. Elevated temperature measurements have indicated a decrease in V TH and an increase in I DS with increasing stress time possibly due to mobile positive ions in the gate dielectric.

Fabrication and characterization of 4H-SiC planar MESFETs

The planar 4H-SiC MESFETs were fabricated by employing an ion-implantation process instead of a recess gate etching process, which is commonly adapted in compound semiconductor MESFETs, to eliminate potential damage to the gate region during etching process. Excellent ohmic and Schottky contact properties were achieved by using the modified RCA cleaning of 4H-SiC surface and the sacrificial thermal oxide layer. The fabricated MESFETs was also free from drain current instability, which the most of SiC MESFETs have been reported to suffer for the charge trapping. The drain current recovery characteristics were also improved by passivating the surface with a thermal oxide layer and eliminating the charge trapping at the surface. The performance of fabricated MESFETs was characterized by analyzing the small-signal equivalent circuit parameters extracted from the measured parameters.

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition.

Sulfide treated GaAs MISFET's with gate insulator of photo-CVD grown P/sub 3/N/sub 5/ film

Sulfide passivated GaAs MISFET's with the gate insulator of photo-CVD grown P/sub 3/N/sub 5/ films have been successfully fabricated. The device shows the drain current instability less than 22% for the period of 1.0 s /spl sim/1.0/spl times/10/sup 4/ s, due to excellent properties of sulfide treated P/sub 3/N/sub 5//GaAs interface. The effective electron mobility and extrinsic transconductance of the device are about 1300 cm/sup 2//V/spl middot/sec and 1.33 mS, respectively, at room temperature. To estimate the effects of sulfide treatment on P/sub 3/N/sub 5//GaAs interfacial properties, GaAs-MIS diodes are also fabricated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

InP double-layer gate MISFET technology for VLSIs

Abstract E/D InP MISFETs with anodic Al 2 O 3 /native oxide double-layer for gate insulator with nanometer thick native oxide layer are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500–3000 cm 2 /V. sec and marked reduction of drain current instability were simultaneously achieved. This is consistent with the interface properties measured by C-V analyses. InP MISFET E/D inverters as well as ring osillators are fabricated to demonstrate the capability of the process employed. The successful stable and high-speed operation of the ring oscillator as well as the inverter indicates great potential of the present technology for LSI/VLSI applications with nanometer device dimensions.

InP MISFET's with Al2O3/Native Oxide double-layer gate insulators

Enhancement-mode InP MISFET's with anodic Al 2 O 3 / native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500-3000 cm2/V . s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements. InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.

Interface Effects on Drain Current Instability in GaAs MESFETs with Buffer Layer

Interface effects on drain current instability in GaAs MESFETs with buffer layer were investigated by applying DLTS technique to the drain current transients. The measurements revealed that the instability is due to deep acceptors or hole traps, which exist at the interfaces and in the buffer layer and the semi-insulating substrate. Five kinds of deep levels were found for three groups of FETs. Particularly it was clarified that the long-term drift in the drain current is attributed to Cr in the buffer layer as well as in the semi-insulating substrate.