Reliability of Highly Stable Amorphous-Silicon Thin-Film Transistors Under Low Gate-Field Stress—Part II: Optimization of Fabrication Conditions and Gate Voltage Dependence

Abstract

Part I of this paper introduced a two-stage model for reliability characterization and lifetime prediction of amorphous-silicon thin-film transistors (a-Si TFTs) under low gate-field stress that includes both charge trapping in the silicon nitride (SiNx) gate dielectric and defect generation in the a-Si channel. In part II, the model is used to experimentally reduce the drain current instability under room temperature operation of a-Si TFTs under a prolonged gate bias of 5 V. Deposition conditions for the SiNx gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive-ion-etch steps, or with all wet-etch steps. The stability of the a-Si channel also depends on the deposition conditions for the underlying SiNx gate insulator, and TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% lifetime of the drain current of back-channel-passivated dry-etched TFTs under continuous operation in saturation at 20 °C with $V_{\mathrm{GS}}=\text{5} \text{V}$ from $\text{3}\times \text{10}^{4} \text{s}$ (9.2 h) to $\text{4}\times \text{10}^{7} \text{s}$ (1.4 years). We also extend the model, so that parameters from the degradation at one gate voltage can be used to estimate the degradation at other low gate voltages.