Double-gate Technology Research Articles

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations .

Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Dual-threshold-voltage (VT) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-VT (HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-VT technology options-increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness-is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping.

A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly.

Modeling and Analysis of Leakage Currents in Double-Gate Technologies

This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body asymmetric device with different front and back gate materials. The effect of variations in device parameters on the leakage components is also analyzed. Using the developed models, digital circuits (logic gates and static random access memory cells) designed with different DG structures are also analyzed. The analysis shows that the use of (near mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG devices and circuits

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

Technology and circuit design considerations in quasi-planar double-gate SRAM

SRAM is likely to remain the largest, leakiest, and most process-sensitive circuit block on chip. FinFET, a width-quantized, quasi-planar, double-gate technology, has emerged as the most likely candidate to replace classical technologies around the 45-nm node. This paper studies the impact of FinFET design choices on device and SRAM circuit metrics to understand how its unique properties can be suitably harnessed. Width-quantization limits SRAM sizing choices, while quasi-planarity allows increased cell current by increasing fin height. Conversely, the latter property can be exploited to increase V/sub t/ and/or decrease V/sub dd/ to achieve exponential leakage savings at constant area and read access time. We explore both approaches to selecting the right combination of device structure, V/sub t/ and V/sub dd/ that achieves maximum stability and minimum leakage over the design space. Increasing V/sub t/ with fin height and body thickness improves stability, decreases variability, and decreases source-drain leakage exponentially. But this necessitates the use of small t/sub ox/ to control short channel effect; this increases gate leakage exponentially. On the other hand, increasing V/sub t/ and decreasing V/sub dd/ allows the use of larger t/sub ox/ to maintain short-channel effect and control gate leakage; however, this worsens stability. Careful co-design of device structure, V/sub t/ and V/sub dd/ is imperative to optimize SRAM metrics.

Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits

Leakage power and input pattern dependence of leakage for extremely scaled (L/sub eff/=25nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications. Unique DG device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for DG CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for DG device, considering state dependency, show that leakage currents for DG circuits are reduced by a factor of over 10/spl times/, compared with bulk-Si counterpart.

A 1-µm Mo—poly 64-kbit MOS RAM

This paper describes a 1-µm 64-kbit MOS RAM using Mopoly technology. New 1-µm double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-µm Si-gate FET's in peripheral circuitry. A 1-µm Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1-µm process technologies. The cell size and die size were 8 µm × 8 µm and 3 mm µ 3 mm, respectively. Access time was less than 100 ns.

A 1-/spl mu/m Mo-Poly 64-Kbit MOS RAM

This paper describes a 1-m 64-kbit MOS RAM using Mo-poly technology. New 1-/spl mu/ m double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-/spl mu/ m Si-gate FET's in peripheral circuitry. A 1-/spl mu/ m Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1/spl mu/ m process technologies. The cell size and die size were 8 /spl mu/ m X 8 /spl mu/ m and 3 mm X 3 mm, respectively. Access time was less than 100 ns.