Dopant-segregated Schottky Barrier MOSFETs Research Articles

Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current

In this paper, to solve the problem of higher ambipolar leakage current (Iambipolar) of Dielectric Engineered (DE) Dopant Segregated (DG) Schottky Barrier (SB) MOSFET (DE DS SBMOS), we have incorporated dual metal gate (DMG) in place of single metal gate for the DE DS SBMOS. The proposed device is named as DMG DE DS SBMOS. In a proposed device, the gate is consisting of dual metal having different work functions. Therefore, the gate is divided in two parts named as auxiliary gate (AG) and tunneling gate (TG). AG and TG employed near the source and drain (S/D) ends, respectively. AG is mainly used to control the on-state performance and TG for the off-state performance by modulating the SB height and width at S/D end, respectively. Simulation results show that Iambipolar of the device has been successfully suppressed by choosing appropriate work functions for AG and TG without affecting the on-state current (Ion) of the device. The proposed device combines the advantage of dual metal gate and dielectric engineering to achieve improvement in the overall performance of the device. The proposed device exhibits high Ion, low Iambipolar and low subthreshold swing (SS). The simulations study verifies the use of the proposed device for low power applications.

Design and Investigation of Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With NiSi Source/Drain

In this paper, to solve an important issue of low ON-state current in the nickel silicide (NiSi) metal source/drain Schottky barrier (SB) MOSFET (SBMOS), we have reported a novel dielectric engineered (DE) dopant segregated (DS) SBMOS structure using gate dielectric engineering. In a proposed device, we employ two different gate dielectric materials. The high-k gate dielectric is used at the source side and low-k gate dielectric at the drain side. Beneath the high-k gate dielectric, electron accumulation increases due to large gate dielectric capacitance density. As a result, reduction in depletion of source side dopant segregation layer further decreases the SB tunneling width for the electron injection. Consequently, improvement in ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is obtained. In addition, the low-k gate dielectric and drain side dopant segregation layer increases the effective SB height and tunneling width for the hole injection. Thus, the OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) is suppressed. The optimization of proposed device has been performed by modulating the length of high-k and the low-k gate dielectric. In addition, we have compared the performance of the proposed device in terms of ON to OFF current ratio $({I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}})$ , subthreshold swing (SS), transconductance $({g}_{ {m}})$ , transconductance generation factor $({g}_{ {m}}/{I}_{ {D}})$ , cut-off frequency $({f}_{ {T}})$ , and gain-bandwidth product $({f}_{ {A}})$ to the SBMOS, DS SBMOS, and DS SBMOS with the full high-k gate dielectric. Moreover, we have proposed the possible process flow for the DE DS SBMOS fabrication.

Operation and scalability of dopant-segregated Schottky barrier MOSFETs with recessed channels

Recessed channels were used in scaled dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to control the severe short-channel effect. The physical operation and device scalability of the DS-SBMOS resulting from the presence of recessed channels and associated gate-corners are elucidated. The coupling of Schottky and gate-corner barriers has a key function in determining the on–off switching and drain current. The gate-corner barriers divide the channel into three regions for protection from the drain penetration field. To prevent resistive degradations in the drive current, an alternative asymmetric recessed channel (ARC) without a source-side gate-corner is proposed to simultaneously optimize both the short-channel effect and drive current in the scaled DS-SBMOS. By employing the proposed ARC architecture, the DS-SBMOS devices can be successfully scaled down, making them promising candidates for next-generation CMOS devices.

CMOS Inverter Based on Schottky Source–Drain MOS Technology With Low-Temperature Dopant Segregation

This letter demonstrates the integration of complementary dopant-segregated Schottky barrier MOSFETs into CMOS inverters. The implementation of a valence-band-edge silicide, namely, PtSi, associated to arsenic (As) and boron (B) low-temperature segregation is validated for the first time at the circuit level. Current drives for n- and p-type devices are Ion = 596/378 μA/μm at Vds = |1.1 V| and |Vgs| = 2 V to account for the 2.4-nm gate oxide thickness. Excellent inverter voltage transfer characteristics, large voltage gain, and appreciable noise margins have been obtained down to 0.5 V of supply voltage.

Dopant-segregated Schottky barrier MOSFETs with an insulated dielectric oxide

An insulated dielectric oxide (IDO) is presented for the dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to suppress the unwanted on- and off-state leakage currents in short-channel DS-SBMOS. The effects of the IDO on DS-SBMOS are investigated using two-dimensional device simulations. Although the dopant segregation technique can efficiently modify a Schottky barrier to improve Schottky barrier MOSFETs, the performance of scaled DS-SBMOS suffers from degraded short-channel behavior and ambipolar conduction from the extension of a heavily doped segregation layer. With sidewall IDO insulators between the heavily doped N+ segregation layer and P+ halo region, band-to-band and ambipolar leakage currents are simultaneously minimized. Thus, an optimal halo can be utilized to control the short-channel effect without any constraints in problematic leakage currents. Using the IDO architecture, DS-SBMOS can be successfully scaled as a promising candidate for next-generation CMOS devices.

A Computational Study of Dopant-Segregated Schottky Barrier MOSFETs

A dopant-segregated Schottky barrier MOSFET is simulated by Monte Carlo method in this paper. The feature that dopant-segregated structure can improve on-current is revealed. The influence of dopant-segregated structure parameters on device performance is investigated, and the guideline for device design optimization is that the dopant-segregated region should overlay the whole Schottky barrier region. Some carrier transport details are also demonstrated here. The maximal velocities at source and drain sides all decrease with the increase of dopant-segregated region length. The maximal velocity at source side shows saturation with the existence of dopant-segregated structure when drain voltage increases while the maximal velocity at drain side shows no saturation.

Device considerations and design optimizations for dopant segregated Schottky barrier MOSFETs

This work thoroughly explores the considerations and optimizations of dopant segregated Schottky barrier MOSFETs (DS-SBMOS) using two-dimensional device simulations. The dependences of the device characteristics on the dopant segregated layer are clarified in the DS-SBMOS. The heavier and wider dopant segregation layer efficiently modifies the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, DS-SBMOS devices have slightly worse short-channel effects than conventional MOSFETs, because of additional segregation extensions into the silicon substrate. Importantly, apparent degradations of DS-SBMOS in ambipolar conduction are observed when a thinner gate-insulator or a heavier halo profile is used for the scaled short-channel DS-SBMOS. Dual workfunction gate (DWG) architecture is first proposed to optimize DS-SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal design of DS-SBMOS devices can be achieved using the DWG structure with enhanced driving current, minimized ambipolar conduction and a suitable short-channel effect as the gate-insulator is scaled down.