Dopant Fluctuation Research Articles

III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance

In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and high thermal budgets and streamlines the fabrication. The implementation of III–V compound material, i.e. low bandgap compound GaSb, in the source region, combined with the larger area gate normal line tunneling, improves the ON current for our proposed III–V JF L GNLTFET device. Additionally, the utilization of large bandgap GaAs compounds on the drain and channel sides eliminates ambipolarity and further enhances the performance of our proposed device. Meaning that the proposed device simultaneously improves the ON current and suppresses the ambipolarity. Our proposed III–V JF L GNLTFET exhibits enhanced output performance with an ON current of 23.2 μA μm−1 and a minimum and average subthreshold swing of 3.7 mV dec−1 and 15.82 mV dec−1 respectively. Furthermore, the proposed III–V JF L GNLTFET also gives superior RF/analog performance with transconductance (168.65 μS), cut-off frequency (33.52 GHz), gain-bandwidth product (5.11 GHz), and transconductance-frequency product (243.7 GHz).

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

Study of Process Variation in Nanotube Tunnel Field Effect Transistor

In the nanoscale, the process parameters and device dimension variation extensively affect the electrical performance of the device. Therefore, an inclusive study for the prediction of the overall device behavior is extremely necessary. In this manuscript, process variations caused by random dopant fluctuation (RDFs), variation of oxide thickness, and workfunction during fabrication are analyzed in junctionless nanotube TFET. The work quantitatively evaluates the impact of process variability on the various electrical parameters like energy band diagram, electric field, carrier concentration, and drain current of the nanotube TFET structure. The device simulation has been carried out with a 3-D SILVACO ATLAS simulator.

A Comprehensive Analysis of Nanosheet Field-Effect Transistor: Recent Advances and Comparative Study

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability.

Unveiling the reliability of negative capacitance FinFET with confrontation of different HfO2-ferroelectric dopants

The CMOS compatibility of Negative Capacitance (NC) FETs has been enhanced tremendously after introducing a thin film-doped HfO2 as a ferroelectric (FE) layer. For a given FE layer, the NC property is governed by specific HfO2 dopants (e.g., La, Zr, Al, Sr, Gd, Y, and Si). Thus, the TCAD simulation considerably depends on the dopant-specific Landau parameters (αx,βx,γx,ρx,gx), and its solidity needs proper attention. Further, the reliability of the NC devices is severely affected by process variations, i.e., interface trap charges, work function variation, random dopant fluctuation, and ambient temperature (external), which modulates the device threshold voltage (Vth); in turn, the device aging. In this paper, using well-calibrated TCAD models, we investigated reliability for the different dopant-specific NC-FinFET, in terms of Vth, ON current (ION), and OFF current (IOFF) modulation induced by: (i) the interface trap variability (ITV) considering the different trap concentration and energy location; (ii) the work function variability (WFV) considering different metal grain sizes (Gr); (iii) the random dopant fluctuations (RDF); and (iv) the ambient temperature. In this way, the device aging is calculated by inspecting Vth shift by ±50mV. These investigations pave the path for realizing a reliable NC-FinFET design.

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

This work demonstrates the reliability-aware analysis of the Junctionless negative capacitance (NC) FinFET employed as a hydrogen (H2) gas sensor. Gate stacking of the ferroelectric (FE) layer induces internal voltage amplification owing to the NC property, thus, improving the sensitivity of the baseline junctionless FinFET. A well-calibrated TCAD model is used to investigate the sensing characteristics of the proposed FinFET-based H2 sensor by employing the palladium (Pd) metallic gate as a sensing element. The mechanism involves the transduction of H2 gas molecules over the metal gate; due to the diffusion process, some atomic hydrogen diffuses into the metal. The H2 gas absorption at the metal surface causes a dipole layer formation at the gate and oxide interface, which changes the metal gate work function. As a result, this change in the work function can be used as a sensing parameter of the proposed gas sensor. Further, the threshold voltage and other electrical characteristics, such as output conductance, transconductance, and drain current are examined for sensitivity analysis for both NC and without NC JL FinFET at different pressure ranges, keeping the temperature constant (i.e. 300 K). The device variation, i.e. Fin thickness, Fin height, doping and thickness of HfO2 ferroelectric layer, etc, on sensor sensitivity has been evaluated through extensive simulation. This paper also presents a detailed investigation of the sensor’s reliability in terms of work function variation, random dopant fluctuation, trap charges, and device aging, i.e. end of a lifetime. At last, the acquired results are compared with earlier reported data, which justifies the profound significance of the proposed junctionless negative capacitance FinFET-based H2 gas sensor.

Investigation of SiGe/Si heterojunction inductive line tunneling TFET with source Schottky contact for prospect ultra-low power applications

In this paper, a SiGe/Si heterojunction inductive line tunneling tunnel field-effect transistor with source Schottky contact (SC HJLT-iTFET) is proposed and investigated by the Sentaurus Technology Computer Aided Design (TCAD) simulator. By utilizing an appropriate source Schottky metal, the need for multiple ion implantation and annealing steps required for traditional P–I–N TFETs can be avoided, and the problems of self-alignment and random dopant fluctuations (RDF) during ion implantation can be solved. A high ON-state current (I ON) is obtained as fully overlapping the source and gate by line tunneling mechanism dominated, the appropriate Si1−x Ge x mole fraction material in the source region and high-k gate dielectric employed can further improve I ON. The incorporation of the block layer effectively decreases the lateral electric field at the drain end to reduce the OFF-state current (I OFF). Furthermore, the proposed charge enhancement layer (CEL) on the SiGe channel can suppress the Fermi level pinning effect (FLP) and enhance the charge of the source region. Based on the feasibility of the practical fabrication process, and the rigorous simulations indicate that the device has an SSavg of 19.8 mV/dec and SSmin of 6.8 mV/dec at V D = 0.2 V, I ON of 2.27 × 10−6 A μ m−1, and an I ON/I OFF ratio of 1.02 × 1010, with extremely fast switching speed. These features make the device suitable for future ultra-low power applications on the internet of things, artificial intelligence, and related fields.

An inverted T-shaped vertical tunneling InN/InxGa1-xN heterojunction TFET with high current ratio

An inverted T-shaped vertical InN/InGaN tunneling field effect transistor (TFET) with polarization-induced doping and high current ratio is proposed and investigated. An optimal structure of the proposed device is given by comparing on-state current, subthreshold voltage, and on-state/off-state current ratio. The polarization effect in III-N material induces electrons and holes in the source and drain regions, and non-physical doping can avoid random dopant fluctuations (RDFs) and high thermal budget. The InN/InGaN heterojunction TFET shows significant improvement over the homojunction TFET. The inverted T-shaped structure involves line and point tunneling simultaneously, so the proposed device can achieve higher on-state current than the conventional device. In addition, the proposed device shows the suppression of ambipolar current. The simulations reveal that the ION/IOFF of the proposed structure is about 6.91 × 1012. These results indicate that the line tunneling structure is still available in the polarization-induced InN/InGaN TFET.

Analytical modelling and reliability analysis of charge plasma-assisted Mg2Si/Si heterojunction doping less DGTFET for low-power switching applications

Fabrication of tunnel field effect transistor (TFET) confronts various challenges, one of which is random dopant fluctuation (RDF), which diminishes the benefits associated with low subthreshold swing (SS) and high ION/IOFF ratio. By conducting physics-based 2D analytical modelling, this paper proposes a magnesium silicide/silicon (Mg2Si/Si) heterojunction-based doping less double gate tunnel field effect transistor (HB-DL-DGTFET). This work utilizes the concept of charge plasma to tackle the issues of RDF. The analytical analysis in this study is based upon the determination of the center-channel potential by solving 2D Poisson’s equation, considering appropriate boundary conditions. Here, surface potential, electric field, energy bands, drain current and threshold voltage are extracted mathematically. In addition to the aforementioned parameters, several other analog performance parameters like transconductance, drain conductance, device efficiency, intrinsic gain, output resistance and channel resistance have also been studied in this context. The analytical findings have been duly validated using the ATLAS TCAD device simulator. Furthermore, this work focuses on exploring proposed device reliability through an investigation of, the influence of interface trap charges (ITC), present at the Si/SiO2 interface. The study analyses ITC's impact on analog performance and the obtained results are compared with that of conventional doping less DGTFET (C-DL-DGTFET). The simulation results reveal that HB-DL-DGTFET exhibits greater immunity against ITC. Thus, validating the potential of HB-DL-DGTFET as a superior candidate for low-power switching applications.

Low-temperature deuterium annealing for improved electrical characteristics of SONOS

Deuterium annealing is a promising process technology for CMOS fabrication. Deuterium annealing effectively passivates interface traps at the Si-SiO2 interface, allowing for improvements in the electrical characteristics and reliability of CMOS. However, conventional deuterium annealing is typically performed at high temperatures above 400 °C, which can lead to unwanted dopant deactivation, random dopant fluctuation (RDF), and thermal-induced stress in the backend-of-the-line (BEOL). In this study, we demonstrate the use of deuterium annealing at low temperatures, resulting in improvements in SONOS devices. Device characterizations based on subthreshold swing (SS), on-state current (ION), off-state current (IOFF), and gate leakage current (IG), as well as time-of-flight secondary ion mass spectrometry (ToF-SIMS) are included to clarify the effects of annealing.

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

Modulation Doping of Silicon Nanowires to Tune the Contact Properties of Nano‐Scale Schottky Barriers

AbstractDoping silicon on the nanoscale by the intentional introduction of impurities into the intrinsic semiconductor suffers from effects such as dopant deactivation, random dopant fluctuations, out‐diffusion, and mobility degradation. This paper presents the first experimental proof that doping of silicon nanowires can also be achieved via the purposeful addition of aluminium‐induced acceptor states to the SiO2 shell around a silicon nanowire channel. It is shown that modulation doping lowers the overall resistance of silicon nanowires with nickel silicide Schottky contacts by up to six orders of magnitude. The effect is consistently observed for various channel geometries and systematically studied as a function of Al2O3 content during fabrication. The transfer length method is used to separate the effects on the channel conductivity from that on the barriers. A silicon resistivity is achieved as low as 0.04–0.06 Ω ·cm in the nominal undoped material. In addition, the specific contact resistivity is also strongly influenced by the modulation doping and reduced down to 3.5E‐7 Ω · cm2, which relates to lowering the effective Schottky barrier to 0.09 eV. This alternative doping method has the potential to overcome the issues associated with doping and contact formation on the nanoscale.

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5μA/μm and Ion/Ioff is 3.2×107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621×105 S/μm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices.

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

In this work, an InGaAs/InAlAs dopingless tunnel field-effect transistor is designed and systematically examined through numerical simulations. In line with the charge plasma concept, the proposed device can not only create a p-n-i-n structure without doping to enhance electron tunneling but also effectively overcome issues caused by doping such as random doping fluctuation, high thermal budget, etc. By investigating the effects of the HfO2 length (L H), the source-side channel length (L sc), and the source-drain electrodes structure on the proposed device, it concludes that the best device characteristic can be acquired when L H is located between 110 nm and 128 nm, L sc=4 nm, and double source-drain electrodes are adopted.

Ionotronic WS2 memtransistors for 6-bit storage and neuromorphic adaptation at high temperature

Inspired by massive parallelism, an increase in internet-of-things devices, robust computation, and Big-data, the upsurge research in building multi-bit mem-transistors is ever-augmenting with different materials, mechanisms, and state-of-the-art architectures. Herein, we demonstrate monolayer WS2-based functional mem-transistor devices which address nonvolatility and synaptic operations at high temperature. The ionotronic memory devices based on WS2 exhibit reverse hysteresis with memory windows larger than 25 V, and extinction ratio greater than 106. The mem-transistors show stable retention and endurance greater than 100 sweep cycles and 400 pulse cycles in addition to 6-bit (64 distinct nonvolatile storage levels) pulse-programmable memory features ranging over six orders of current magnitudes (10−12–10−6 A). The origin of the multi-bit states is attributed to the carrier dynamics under electrostatic doping fluctuations induced by mobile ions, which is illustrated by employing a fingerprint mechanism including band-bending pictures. The credibility of all the storage states is confirmed by obtaining reliable signal-to-noise ratios. We also demonstrate key neuromorphic behaviors, such as synaptic plasticity, near linear potentiation, and depression, rendering it suitable for successful implementation in high temperature neuromorphic computing. Furthermore, artificial neural network simulations based on the conductance weight update characteristics of the proposed ionotronic mem-transistors are performed to explore the potency for accurate image recognition. Our findings showcase a different class of thermally aided memories based on 2D semiconductors unlocking promising avenues for high temperature memory applications in demanding electronics and forthcoming neuromorphic computing technologies.

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source and drain regions. Due to its doping-less structure, the proposed CP-ITSM-DLTFET is immune to random dopant fluctuations and does not require an expensive thermal annealing technique. This makes the proposed device’s fabrication easier and more efficient. The proposed CP-ITSM-DLTFET comprises an inverted T-shaped source metal (sandwiched between the Si-channel) and creates gate-to-source overlap and increases the tunneling area vertically on both sides of the Si-channel. The vertical line-tunneling area in the proposed structure makes the device able to be aggressively scaled compared to conventional TFETs for future technology. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. The switching performance (like high ION = 31.88 uA um−1, steeper AVSS = 23.42 mV dec−1 (over 12-order of drain current), and high ION/IOFF ratio of 1.6 × 1013) and the RF performance (like transconductance (gm) = 0.37 mS, Cut-off frequency (fT) = 90.18 GHz, and Gain Bandwidth product (GBW) = 32.3 GHz) of the proposed CP-ITSM-DLTFET are superior to almost all pre-existing Si, SiGe, and Ge based doping-less TFETs. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter has also been comprehensively studied in the paper, showing a good noise margin NMH = 0.198 V (39.8% of VDD) and NML = 0.206 V (41.2% of VDD) with a high voltage gain of 30.25 at VDD = 0.5 V, suggesting great potential for future low power applications.

A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement

This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

Endurance Behavior of Z-Shaped Charge Plasma Tunnel FET for Biosensing Application

The tunneling field effect transistor (TFET) is a viable candidate for designing a highly sensitive biosensor. In this work, a doping-less Z-shaped dielectrically modulated charge plasma TFET (CPTFET) structure with misaligned cavity region on channel and source has been proposed for label-free biosensing applications. To design the device, charge plasma technique has been employed, where appropriate metal workfunction is used over intrinsic silicon to create n[Formula: see text] drain and p[Formula: see text]source regions. The charge plasma approach reduces thermal budget, random dopant fluctuation (RDF) and steps required for fabrication. The Z-shaped CPTFET includes the advantage of abrupt profile of doping at source-channel (tunneling) junction. Because cavities are created in source and gate oxide region, the abrupt doping profile suppresses ambipolar behavior and improves sensitivity. The performance of the proposed device for both charged and neutral biomolecules in terms of electric field, band energy, transfer characteristics, [Formula: see text] ratio and subthreshold swing (SS) has been examined. The response of other parameters like cavity thickness and cavity length on ON current has been analyzed using the Silvaco ATLAS device simulator.

A label-free dielectric-modulated biosensor using SiGe-heterojunction dual cavity dual metal electrically doped TFET

The detection of biomolecules has been accomplished in this article by using the tunnel field effect transistor’s (TFET) bipolar nature. The fabrication procedure has been made simpler, the prices have gone down, and random dopant fluctuation (RDFs) have been eliminated using the charge plasma concept. The objective of this work is to investigate the performance of a DopingLess- Dual Metal Gate- Dual Cavity- HeteroJunction- Tunnel Field Effect Transistor (DL-DMG-DC-HJ-TFET) biosensor that can sense biomolecules in both the ON and ambipolar states. It is feasible to recognize many types of biomolecules concurrently by taking into account the cavities at both tunneling junctions. The suggested biosensor’s OFF state current has been reduced and its sensitivity has been increased via the use of gate workfunction engineering and bandgap engineering. It has been investigated how the presence of proteins in the cavities affects electrical properties such as energy band diagram (EBD), surface potential (SP), subthreshold Swing (SS), threshold voltage , and current ratio The impact of temperature, germanium mole fraction, and position of biomolecules is also analyzed in this work. A comparative analysis for drain current sensitivity is presented considering different previous works.

Analysis of III-V material-based dual source T-channel junction-less TFET with metal implant for improved DC and RF performance

In this paper, two III-V material-based junctionless tunnel FET devices, D-1 and D-2, are proposed. The proposed device D-1 has a low bandgap (GaSb-based) dual source and a higher bandgap (GaAs-based) T-channel junctionless, and the proposed device D-2 has the same architecture as D-1 in addition to a metal strip implant in the gate oxide near both source regions. Due to junctionless architecture, the proposed D-1 and D-2 eliminate random dopant fluctuations (RDF), remove the need for high thermal budgeting, and give better performance with less variability. The wide bandgap (GaAs) T-channel and the drain region formed far from the gate fully suppress the ambipolarity for both the proposed D-1 and D-2. The low-bandgap GaSb material in the source improves the ON current for D-1 and D-2. Compared to the conventional junctionless TFET (JL-TFET), the proposed D-2 (even at a lower bias of 0.5 V) improves the ON current by 1.7 times and the ION/IOFF ratio by 216.66 times, with a much-reduced average subthreshold swing value of 32.7 mV/dec compared to 70 mV/dec of the conventional JL-TFET. Furthermore, the proposed D-2 also provides much improved RF performance with a higher transconductance (gm) of 147.8 μs, higher cut-off frequency (fT) of 32.26 GHz, a higher gain-bandwidth product (GBW) of 3.52 GHz, higher transconductance-frequency product (TFP) of 286 GHz, and a lower transit time (τ) of 5 × 10–12 s. Furthermore, we analyze various linearity parameters such as gm2, gm3, VIP2, VIP3, IIP3, and IMD3 for both D-1 and D-2, and our findings indicate that D-2 exhibits improved linearity performance.