In this paper theoretical benchmarking of semi-vertical and vertical gallium nitride (GaN) MOSFETs with rated voltage of 1.2 kV to 3.3 kV is performed against corresponding silicon carbide (SiC) devices. Specific design features and technology requirements for realization of high voltage vertical GaN MOSFETs are discussed and implemented in simulated structures. The main findings are that a) specific on-resistance of vertical GaN devices is expected to be 75% and 40% of that for 1.2 kV and 3.3 kV SiC MOSFETs, respectively, b) semi-vertical GaN do not offer any advantage over SiC MOSFETs for medium and high voltage devices (>1.0 kV), and c) vertical GaN has largest potential advantage for high and ultra-high voltage devices (>2.0 kV).Gallium nitride (GaN) devices experience an explosive and rapid development with new device providers entering the market at an impressive speed. However, the devices are HEMT (High Electron Mobility Transistor) type lateral devices utilizing the two-dimensional electron gas (2DEG) properties of the GaN/AlGaN interface. The required GaN layers in the devices are grown epitaxially on hetero substrates like Si, SiC, sapphire and poly-AlN using buffer layers to control the strain caused by lattice mismatch which prevents the vertical current flow. For power applications the lateral current flow close to the surface leads to thermal limitations and complicates thermal management in packaging. Furthermore, it leads to large footprint of the devices for large currents. The devices also lack the robust avalanche breakdown characteristics. At present the HEMT power devices are limited to operational voltages of less than 650V with some first devices from VisIC and iGaNPower demonstrating 1200V capability. For these reasons there is an interest in the development of vertical GaN devices opening the possibilities of small footprint and thus lower cost due to smaller chip sizes, high power densities and robust avalanche breakdown characteristics with large avalanche energy capability [1]. The development of vertical devices has been hindered by the lack of large area freestanding GaN substrates facilitating homoepitaxial growth of drift layers. An alternative are semi-vertical structures grown on Si which are the subject of this study along with true vertical structures on GaN. In addition to the material issues there are technological issues that require further attention like dopant compensation and activation and Mg implantation technology for junction termination. This paper focuses on prospective benchmarking of semi-vertical and vertical GaN MOSFETs against SiC devices. A beyond the state-of-the-art benchmarking, in wide voltage range, is missing in the literature. Most of the benchmarking publications report results of experimental structures based on state-of-the-art technology and simple junction termination [2], [3], [4].The main objective of the work has been to design competitive semi-vertical and vertical GaN structures and perform benchmarking against SiC devices in the voltage range 1.2 kV to 3.3 kV. The structures have been characterized by calculating the output, transfer and voltage blocking characteristics using default Sentaurus models. In the next step, the structures have been modified based on the experience and know-how from SiC devices. The electric field crowding occurring at the trench gate corners must be mitigated both with respect to the breakdown voltage in the bulk material and the reliability of the gate dielectric [5]. Efficient junction termination (JT) is also necessary for both types of structures. This is especially important in the semi-vertical structures where junction termination is an integral part of each device segment and has a significant impact on the resulting on-state resistance. The structure design was optimized by reducing the cell pitch and introducing a multi-cell-per-device-segment design in semi-vertical structures to improve the on-resistance. Removal of the performance limitations in the structures based on the state-of-the-art GaN technology and device cell optimization was done to make benchmarking with more mature SiC devices based on the prediction of what may become feasible beyond the state-of-the-art.1. Matteo Meneghini et al., Journal of Applied Physics, vol. 130, p. 181101, 2021.2. Oka, T. Ina, Y. Ueno and J. Nishii, 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 303-306, 2021.3. A. Khadar, C. Liu, R. Soleimanzadeh and E. Matioli, IEEE Electron Device Letters, vol. 40, no. 3, pp. 443-446, 2019.4. Wei He et al., Nanoscale Research Letters, 17:14, 2022.5. Nakamura et al., 2011 International Electron Devices Meeting, pp. 26.5.1-26.5.3, 2011.
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