DMA Controller Research Articles

The SUPRENUM vector floating-point unit

The paper describes the implementation of a high-performance 64-bit vector floating-point unit. This implementation consists of a microcontroller, coprocessor interface (for the 68020), DMA controller, various specialised memories, and the Weitek floating-point processors.

The design of a custom chip set for the ALEPH event builder at LEP

This paper describes the design and implementation of two custom integrated circuits for a Fastbus module to be used in the data acquisition system of the ALEPH experiment at LEP. The aim of this project was to replace a large number of conventional circuits in a DMA controller and to reduce the board size needed. The architecture of the circuit is explained, together with a brief discussion of the tools used. A brief cost analysis comparing the ASIC technology with a traditional approach is given.

Fast DMA controller for the VMEbus

A DMA controller can perform autonomous burst data transfers without the intervention of the system processor. As the speed of memory and mass storage devices increases, so does the need for a DMA controller which allows high-speed transfers over the VMEbus. Special attention has to be paid to bus bandwidth to allow optimum access to the VMEbus for all bus master devices. The paper describes the design of a DMA controller with synchronous control logic based on state machines. A synchronous system is easier to design and support than an asynchronous one, although it introduces the problem of synchronization with the signals of the asynchronous VMEbus. A high clock rate provides the necessary speed for the system.

Advanced DMA controller for 16-bit microcomputer systems

The features of a DMA device designed for use with 286, 186, 086 and 088 Intel-type buses are given. The SAB 82258 is also an I/O controller. The principles of data transfer in various modes are detailed, with some examples of data transfer which may be controlled or modified to suit various environments. Methods of interfacing with a CPU are outlined. This includes programming and the use of the multiplexer channel.

Floppy Disk Data Transfer Techniques

Many microcomputer systems use a DMA controller between the floppy disk controller and the CPU. This additional hardware may not always be necessary.

The 3B20D Processor & DMERT Operating System: 3B20D Central Processing Unit

The 3B20D Processor has been developed to meet the need for very reliable, real-time control of a variety of Bell System applications. To achieve its high-reliability goals, most of the major subsystems within the processor are duplicated, including the Central Processing Unit (CPU). The CPU uses a 32-bit architecture throughout, including the memory and input/output buses. Extensive self-checking logic is employed. The 3B20D CPU is microprogrammed to select dynamically up to four instruction sets. The microstore uses a 64-bit word with up to 16K words of high-speed bipolar PROM or RAM available. This rich emulation capability makes the 3B20D Processor ideal for emulating existing instruction sets and porting existing software. Peripheral units are connected to the CPU via the Direct Memory Access unit (DMA). The DMA controllers provide direct memory transfers between the main store and peripheral devices, reducing the load placed on the central control to process input/output requests.

DMA controller adds muscle to offload microprocessor : David MacMillan. Electronics, 147 (10 February 1983)

DMA controller adds muscle to offload microprocessor : David MacMillan. Electronics, 147 (10 February 1983)

High Bandwidth FASTBUS Based Data Acquisition System for Imaging Coronary Arteries

This paper describes the construction of a data acquisition system which will support a minimally invasive replacement for coronary catheterization, generating digitized images of blood flow in the coronary arteries with the aid of a venous injection of x-ray contrast medium. Images generated by a Hamamatsu C1800 TV camera viewing a CGR x-ray image intensifier are digitized by an Analog Devices/Computer Labs MOD-1020/7120 10-bit 20 MHz ADC and then routed to a VICOM model 1500 digital image processing system. Discusses functional specifications and system design. Points out that the FASTBUS system contains three basic items which are interfaced to a single standard FASTBUS crate: a VAX host interface; 64 megabytes of commercial bulk memory; and a DMA controller for moving data from the VICOM into the bulk memory.

海面反射雑音のデータ収録と処理装置

This paper describes a radar signal recorder and a signal analysis system. The system is constructed by (1) sample/hold unit by using CCD, (2) A/D converter and DMA controller and (3) signal analysis unit by using micro processor. The second section of this paper describes the system construction and the examples of operation. The third section will describe the examples of analysis by using of micro processor.