Threshold Voltage Distribution Research Articles

Effects of Heavy-Ion Irradiation on Vertical 3-D NAND Flash Memories

The effects of heavy-ion irradiation on 3-D NAND flash memory cells are investigated. Threshold voltage distributions are studied before and after exposure, as a function of the linear energy transfer, fluence, and irradiation angle. Shifts are smaller in 3-D devices than those in planar ones, for the same equivalent bit density. The cell circular shape and the fact that the tunnel oxide and interpoly dielectric blocking layers are perpendicular to the semiconductor substrate make it possible to gain insight into the underlying upset mechanism, which cannot be obtained with planar devices. Evidence that energy deposition in the blocking oxide layer can contribute to charge loss from the floating gate is presented.

Switching synchronization in one-dimensional memristive networks: An exact solution.

We study a switching synchronization phenomenon taking place in one-dimensional memristive networks when the memristors switch from the high- to low-resistance state. It is assumed that the distributions of threshold voltages and switching rates of memristors are arbitrary. Using the Laplace transform, a set of nonlinear equations describing the memristors dynamics is solved exactly, without any approximations. The time dependencies of memristances are found, and it is shown that the voltage falls across memristors are proportional to their threshold voltages. A compact expression for the network switching time is derived.

Investigation of Retention Characteristics for Trap-Assisted Tunneling Mechanism in Sub 20-nm NAND Flash Memory

In this paper, retention characteristics of the trap-assisted tunneling (TAT) mechanism are investigated in sub 20-nm NAND flash memory. Total charge loss source for the TAT mechanism (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th(TAT)</sub> ) becomes larger with baking temperature, while the source for the detrapping mechanism is almost constant. This temperature dependence of the TAT mechanism becomes larger as program/erase cycling stress increases. Also, this trend is much larger in the highest programmed threshold voltage distribution state. By comparing activation energies of the TAT and the detrapping mechanisms, it was found that the TAT mechanism is very affected by trap density as well as the strength of the electric field in the tunneling oxide layer. To scale down, lifetime of the device can be rapidly reduced due to the decreased time-constant (τ) of the TAT mechanism.

Effects of Liner Thickness on the Reliability of AgTe/TiO2-Based Threshold Switching Devices

The effects of liner thickness on the reliability of AgTe/TiO2-based threshold switching (TS) devices were investigated. The off-state current of an AgTe/TiO2/Pt TS device was found to be significantly increased by in-diffusion of Ag into the TiO2 layer during the annealing process. Therefore, 3-, 5- and 7-nm TiN liners were introduced and compared to prevent the in-diffusion of Ag. While the 3-nm TiN liner was shown to be incapable of blocking Ag in-diffusion into the TiO2 layer, the 5- and 7-nm liners effectively suppressed in-diffusion and maintained high off-state resistance. However, the TS device with the 7-nm TiN liner exhibited wide threshold voltage distribution and poor endurance characteristics owing to a lack of Ag sources. The TS device with a 5-nm TiN liner, by contrast, was found to have an adequate amount of Ag sources and to demonstrate thermally stable and electrically reliable characteristics. The effects of TiN liner on Ag diffusion were also directly confirmed using energy dispersive spectrometry line profiles, transmission electron microscopy imaging, and mapping analyses.

Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices

Charge trapping flash memory devices are susceptible to charge loss mechanisms induced by high energy irradiation such as thermal neutrons, X-rays, and gamma ray. The loss of trapped charges due to charge loss mechanism has resulted in the degradation in data retention performance and unwanted read failures in field applications. In this work, charge loss mechanisms of nanoscale nitride based charge trapping flash memory devices due to irradiation of high energy X-rays were carefully studied and examined. Nitride based charge trapping flash memory device stored charges in the nitride storage layer of an Oxide-Nitride-Oxide stack. Threshold voltage of the nitride based charge trapping flash memory cells were collected before and after X-ray irradiation done onto the memory devices. Threshold voltage distributions have shown that significant number of cells at the lower end of the program distribution had perturbed from the overall distribution that was caused by X-ray irradiation induced charge loss mechanism. In this study, the effect of the use of 300μm Zn filter and its proximity to the device under study to mitigate the X-ray irradiation induced charge loss was also thoroughly elucidated. The results have demonstrated that 300μm Zn filter has significantly improved the immunity of nitride based charge trap flash memory device up to 6.446 times. However, the proximity of the Zn filter to the flash memory device exacerbated up to 7.4280 times due to the impact of secondary effect in X-ray fluorescence to the device under study. Hence, this investigation concluded that X-ray irradiation is a genuine reliability concern for nanoscale nitride based charge trapping flash memory devices. Furthermore, it is recommended to place Zn filter close to X-ray source to significantly mitigate the Vt distribution drift induced by X-ray irradiation.

The Effects of Taper-Angle on the Electrical Characteristics of Vertical NAND Flash Memories

The effects of taper angle of the string and the number of layers on the electrical characteristics of vertical NAND flash memories are investigated. Simulation results show that the transconductance and the threshold voltage distribution over the position of the cell along the string depend on taper angle and the number of layers. There is a taper angle that minimizes the spread of threshold voltage, and hence, the impact of the random telegraph noise and this angle depends on the number of layers. These results will be helpful in designing the vertical NAND flash memories.

Surface Engineering of ITO Substrates to Improve the Memory Performance of an Asymmetric Conjugated Molecule with a Side Chain

Organic multilevel random resistive access memory (RRAM) devices with an electrode/organic layer/electrode sandwich-like structure suffer from poor reproducibility, such as low effective ternary device yields and a wide threshold voltage distribution, and improvements through organic material renovation are rather limited. In contrast, engineering of the electrode surfaces rather than molecule design has been demonstrated to boost the performance of organic electronics effectively. Herein, we introduce surface engineering into organic multilevel RRAMs to enhance their ternary memory performance. A new asymmetric conjugated molecule composed of phenothiazine and malononitrile with a side chain (PTZ-PTZO-CN) was fabricated in an indium tin oxide (ITO)/PTZ-PTZO-CN/Al sandwich-like memory device. Modification of the ITO substrate with a phosphonic acid (PA) prior to device fabrication increased the ternary device yield (the ratio of effective ternary device) and narrowed the threshold voltage distribution. The crystallinity analysis revealed that PTZ-PTZO-CN grown on untreated ITO crystallized into two phases. After the surface engineering of ITO, this crystalline ambiguity was eliminated and a sole crystal phase was obtained that was the same as in the powder state. The unified crystal structure and improved grain mosaicity resulted in a lower threshold voltage and, therefore, a higher ternary device yield. Our result demonstrated that PA modification also improved the memory performance of an asymmetric conjugated molecule with a side chain.

Mitigating Stuck Cell Failures in MLC NAND Flash Memory via Inferred Erasure Decoding

The multilevel-cell NAND flash memory experiences permanent hard errors due to cell defects (stuck cells). To overcome this problem, stuck cells are either regarded as erasures by the decoder based upon the knowledge of stuck cell location, or the entire memory block containing the stuck cells is marked as bad block and made unavailable for future usage. In this paper, a multiround inferred stuck-cell erasure belief-propagation (BP) decoding (ISED) is proposed in which the stuck cell locations are assumed to be unknown to the decoder. To perform the inferred erasure decoding, the input channel log-likelihood ratio (LLR) information is attenuated before BP decoding by modifying the threshold voltage distribution functions. In case of decoding failure, the probable stuck cell locations are inferred by using the flash’s read-back voltage signal and the decoded code-word bits. For all such inferred stuck cells, the input LLRs are set to zero for subsequent rounds of BP decoding. As the likely incorrect LLRs corresponding to the stuck cells are erased, the performance of BP decoder is substantially improved. Simulation results show that the error-rate performance is improved by more than two orders of magnitude with a moderate increase in decoding complexity under the proposed ISED scheme.

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High-dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time-independent process-induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in BTI degradation. Since time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time-zero variability on all of these effects simultaneously. Accordingly, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000nm2) in 30nm technology, we observe significant effects of Random Dopant Fluctuation (RDF) on BTI-induced variability (σΔVth). In addition, circuit analysis reveals similar trend in performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on Vth degradation cannot be disregarded in scaled technology and needs to be considered in variation-tolerant circuit design.

Operating mechanisms of highly-reproducible write-once-read-many-times memory devices based on graphene quantum dot:poly(methyl silsesquioxane) nanocomposites

Resistive switching memory devices were fabricated utilizing graphene quantum dot (GQD):poly(methyl silsesquioxane) (PMSSQ) hybrid nanocomposites. Current-voltage curves for the Al/GQD:PMSSQ/indium-tin-oxide devices at room temperature showed write-once-read-many-times memory (WORM) characteristics with an ON/OFF ratio of as large as 106 due to the homogeneous dispersion of the GQDs in the PMSSQ matrix. The WORM devices maintained retention times larger than 2 × 104 s under ambient conditions. The devices showed high device-to-device reproducibility with threshold-voltage distributions between 3 and 5 V. The ON state currents remained between 10−6 and 10−3 A, and the OFF state currents maintained between 10−12 and 10−9 A. The operating mechanisms concerning the interaction between the GQDs and the PMSSQ matrix for the resistive-switch phenomenon were analyzed on the basis of the I–V results and with the aid of the energy band diagram.

Random telegraph noise on the threshold voltage of multi-level flash memory☆☆Project supported by the National Research Program of China (Grant No. 2016YFB0400402), the Natural Science Foundation of Jiangsu Province, China (Grant No. BK20141321), and the National Natural Science Foundation of China (Grant No. 61627804).

We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation () and the distribution due to RTN increase with the programmed level () of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory

NAND flash memory is a widely used storage medium that can be treated as a noisy channel. Each flash memory cell stores data as the threshold voltage of a floating gate transistor. The threshold voltage can shift as a result of various types of circuit-level noise, introducing errors when data are read from the channel and ultimately reducing flash lifetime. An accurate model of the threshold voltage distribution across flash cells can enable mechanisms within the flash controller that improve channel reliability and device lifetime. Unfortunately, existing threshold voltage distribution models are either not accurate enough or have high computational complexity, which makes them unsuitable for online implementation within the controller.

Modeling of Threshold Voltage Distribution in NAND Flash Memory: A Monte Carlo Method

NAND flash reliability (both endurance and retention) degrades with the scaling of NAND flash memory technology and the introduction of multilevel cell (MLC) and triple-level cell (TLC) technologies. As a result, stronger error correction code (ECC) methods are required in the solid-state drive application, especially for MLC and TLC flash memory devices. Modeling of the threshold voltage ( $V_{t}$ ) distribution in the NAND flash memory can make the ECC simulations more effective and efficient. In this paper, we show a semiphysical and Monte Carlo method to generate a reallike $V_{t}$ distribution by mimicking the NAND flash programming and data retention (DR) processes. Probability distributions used in the Monte Carlo method are obtained by the measurements of the NAND devices and data interpolation or extrapolation. Simulations by this model can obtain reallike $V_{t}$ distribution for any given Program/Erase cycle and DR time. Excellent results have been obtained and confirmed by comparing the simulations with the measured data from 16-nm NAND flash devices.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

A Reliable 2T2MTJ Nonvolatile Static Gain Cell STT-MRAM With Self-Referencing Sensing Circuits for Embedded Memory Application

This paper presents a reliable nonvolatile static gain cell made of two transistors and two magneto-tunneling junctions (MTJs) for cache memory application. The wide distribution in the resistance of MTJs in parallel and anti-parallel states and the variations in the threshold voltage of gain cells are overcome by connecting two complementary MTJs and self-reference sensing circuits, respectively. An enhanced sensing margin and immunity to read disturbance are achieved by applying high voltage across the stacked complementary MTJs. The sensing margin of $8\sigma $ is assured after the Monte Carlo simulation using the measured parameters of the MTJ, including a tunneling magneto-resistance of 200%, a 5% distribution of resistance, and a 5% distribution of threshold voltage in the 65 nm standard CMOS process.

Set and Reset Voltage Interdependence in Resistive Switching Memory Cells

Resistive switching (RS) devices are a primary candidate to supplant current NVM memory based on floating gate MOSFET. However, RS devices suffer from broad distributions of set and reset threshold voltages. The state transition from the initial high resistance state (HRS) to a low resistance state (HRS) is called SET process characterized by a critical voltage Vset. A high current passing through the filament can rupture the bridge and restore the HRS state, in a so-called RESET process of the device and characterized by a critical voltage Vreset. Cu/TaOx/Pt memory cells have been fabricated with 16 nm thick oxygen-deficient TaOx formed by e-beam evaporation. The bottom Pt electrode has been deposited by evaporation and patterned by lift-off on a thermally oxidized Si wafer. The top Cu electrode lines were processed in the same way but patterned perpendicularly to the bottom Pt lines. The width of the metal lines varies between 1μm and 35μm. When a positive voltage is applied to the active electrode, Cu cations dissolve in the solid electrolyte and migrate through it. Cu cations are electrochemically reduced on the Pt cathode. As more Cu atoms accumulate, a nanoscale metalic filament (CF) forms at Vset a conductive path between two electrodes. Here, we report a statistical dependence of set voltage, Vset, on the preceding reset voltage, Vreset, for the same device. Such (Vset, Vreset) pairs have been collected for a multitude of devices in resistive RRAM Cu/TaOx/Pt memory arrays. This dependence appears to be linear and is explained in terms of two interlocking mechanisms responsible for the formation and dissolution of the filaments. The Vset~Vreset dependence on a multitude of memory cells can be replicated also on a single device by intentionally varying Vreset values by the application of different linear voltage ramp rates (rr). The latter mechanism is well modeled under the assumption that a critical heat Qcrit deposited locally in the filament triggers the rupturing of the Cu conductive filament. Qcrit can be obtained as a time integral over the instantaneous power p(t)=(rr·t)2/Ron from t=0 till the reset time treset=Vreset/rr. The experimental Vreset data shows a cubic root dependence on the voltage ramp rate in close agreement with the model, i.e. |Vreset|=Vreset,min +γ(rr)1/3. The model predicts also that γ=(3·Qcrit·Ron)1/3, with Ron being the resistance of the on-state and is fully borne out by experiment on several different Ron values. Ron can be controlled by the compliance current Icc during the set operation according to Ron=0.17/Icc. Moreover, from experimental data and model assumptions, we can extract Qcrit to amount to 6μJ per erase operation. A separate mechanism is proposed to explain the impact of Vreset value on the subsequent Vset value, in terms of increased Cu+ ion mobility at high local temperatures just after the reset and the time τdiss needed to dissipate the Qcrit heat. A higher |Vreset| translates then into larger rupturing gap Δ than a low |Vreset| according to Δ=(|Vreset|/Δo)·μCu+·τdiss where Δo is the initial ruptured gap due to high temperature at the most resistive segment of CF caused by Joules heating. Larger rupturing gate translates then to larger Vset~Δ. The Vreset~Vset relation can be used to tighten Vset and Vreset distributions. RRAM suffers from broad natural distributions of Vset and Vreset obtained at fixed ramp rates. In our method, an array of memory cells with large spread of initial Vset values, has been subjected to three different ramp rates: the devices with high Vset have been reset at a lower ramp rate than devices with low Vset values. The moderate Vset values have been subjected to intermediate ramp rate. The effect of such pre-conditioning results in much tighter distribution of Vreset. The subsequent set operation at constant ramp rate leads to a very tight distribution of Vset. Repeated set and reset operations converge on a very tight Vset and Vreset distributions. This means that the conditioning step has to be applied only once. A natural broad distribution has been selected with experimental data consisting essentially of three clusters of Vset values: (i) centered on Vset=1.0V, (ii) centered on Vset=3.8V, and (iii) data lying in-between. For the natural distribution, the mean value and standard deviation are Vset,m=2.5V and σ=1.35V, respectively. The devices of cluster (i) underwent a reset operation at ramp rate 1V/s, the devices of cluster (ii) at a ramp rate of 1mV/s, while devices with natural Vset in-between have been reset at 10mV/s. After this very simple and not further optimized procedure, a very tight (10x tighter) distribution has been obtained with Vset,m=2.13V and σ=0.14V.

Fitting Cells Into a Narrow &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$V_{T}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Interval: Physical Constraints Along the Lifetime of an Extremely Scaled NAND Flash Memory Array

This paper presents an in-depth comparative analysis of the major physical constraints to the width of the threshold-voltage distribution of a state-of-the-art NAND Flash array. The analysis addresses both time-0 placement by program-and-verify algorithms on fresh and cycled arrays and distribution widening during idle/bake periods. Results allow to identify how each physical effect impacts the threshold-voltage distribution as a function of array program conditions, temperature, cycling, and duration of idle/bake periods, providing clear hints for the design of next generation technology nodes.

Modelling and characterization of NAND flash memory channels

The threshold voltage distribution after ideal programming in NAND flash memory cells is usually distorted by a combination of the random telegraph noise (RTN), cell-to-cell interference (CCI), and the retention process. To decide the original bits more accurately in this scenario, a precise channel model shall be utilized on the basis of the measured threshold voltages. This paper aims to characterize these various distortions occurring in multi-level cell (MLC) flash memories. A mathematical description of the overall distribution for the total flash channel distortion is presented. The final threshold voltage distribution for each symbol of MLC flash is also characterized, which is important for calculating the exact soft decisions of cell bits and the application of advanced flash error correction. The results of the theoretical analysis have been validated through Monte Carlo simulations of the flash channel.

Low Energy Signal Processing Techniques for Reliability Improvement of High-Density NAND Flash Memory

High density NAND flash memory employs very fine process technology, such as sub-20 nm process, and multi-level cell data coding. The reduced feature size not only lowers the number of electrons stored at each floating-gate but also increases the cell-to-cell interference (CCI). As a result, the reliability of NAND flash memory has become an important issue that cannot be well solved by only advancing the process technology. In this paper, we present signal processing and error correction techniques that can overcome the reliability problem while minimizing the energy consumption. These techniques include efficient estimation of the threshold voltage distribution, CCI cancellation aware soft-information computation, and low-energy soft-decision error correction. We also include experimental results for the presented techniques.

Electrostatic Sensitivity Test of Semiconductor Device

The electrostatic sensitivity of triode 2SC3358 has been tested by completely step method. By using strict calculation, we have found the damage threshold voltage distribution of CB junction of the semiconductor device observe normal distribution, the confidence interval about average value of the damage voltage under a confidence level at 90% is (1095.6V, 1256.8V) and the standard deviation is 235.7V. The analysis of the distribution of damage probability about electrostatic sensitive device has important significance for improving the reliability of electrostatic sensitive system.