Distributed Arithmetic Technique Research Articles

Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

The efficient architectures of Two-Dimensional (2D) Finite Impulse Response (FIR) filters are proposed for image processing applications. The performance metrics such as power consumption, area, and delay of the architectures can be optimized using VLSI design. The 2D FIR filter architectures can be implemented using parallel or block processing to increase the filter throughput and to prune the number of clock cycles required for image processing. The symmetry in the filter coefficients decreases the number of multipliers, whereas the multiplier block is very complex and a power-consuming block in the filter architecture. In this work, two types of symmetric architectures such as diagonal symmetry and quadrantal symmetry filters are proposed. The remaining multipliers required for the filter architecture are replaced by Distributed Arithmetic (DA) logic. The memory-based DA reduces the LUT size and hence the area, power, and delay are reduced in the filter architecture. Block processing, symmetry, and DA concepts are introduced here to optimize the 2D FIR filter architecture. The proposed architectures are implemented in 45 nm CMOS technology using Cadence Genus Synthesis tools and area, delay, power, Area-Delay Product (ADP), and Power-Delay Product (PDP) results are obtained and compared with state-of-the-art works. The ADP value of the proposed diagonal symmetry architecture is decreased by a maximum of 73.34 %, and a minimum of 20.39 %, and the PDP value is decreased by a maximum of 90.28 %, and a minimum of 21.27 % when compared to the existing works. The ADP and PDP values of the proposed quadrantal symmetry are decreased by a minimum of 23.62 %, and 27.74 % when compared to existing works, respectively.

Digit-Serial DA-Based Fixed-Point RNNs: A Unified Approach for Enhancing Architectural Efficiency.

The next crucial step in artificial intelligence involves integrating neural network models into embedded and mobile systems. This requires designing compact and energy-efficient neural network models in silicon for optimized performance. This article introduces a unified approach for enhancing the architectural efficiency of long short-term memory (LSTM) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two's complement (TC) digit-serial distributed arithmetic (DSDA) technique are presented. The block-circulant matrix-vector multiplications (MVMs) and element-wise multiplications (EWMs) are formulated using TC DSDA. In addition, a fixed-point (FxP) training procedure for quantized LSTM RNNs is considered and validated for speech recognition tasks. Both structures leverage the circular rotation of weights and generate partial products with input digit slices. A new partial-product generator (PPG) and partial-product selector (PPS) designed to work with both unsigned and signed digits is introduced. In Structure I, a nonpipelined MVM is realized with a few PPGs and PPSs, followed by a shift-accumulate unit (SAU). Conversely, in Structure II, a suitably chosen depth-pipelined MVM is achieved with multiple PPGs and PPSs, followed by a shift-to-add tree (SAT). A critical path delay (CPD) analysis for both the proposed structures is also presented. Compared with previous works, post-synthesis results on 28 -nm fully depleted silicon-on-insulator (FDSOI) technology reveal that for a model size of 128 × 128 , Structures I and II provide 39.87% , 95.63% , and 30.95% , 91.18% more area and energy efficiencies, respectively.

Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

Very large scale integration implementation of efficient finite impulse response filter architectures using novel distributed arithmetic for digital channelizer of software defined radio

AbstractAlways an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in software‐defined radio (SDR). In this paper, a block‐based reconfigurable finite impulse response (FIR) filter is proposed using distributed arithmetic (DA) technique. The complexity of the conventional multiplier is replaced with the DA multiplication process, and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the look‐up tables (LUTs) concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using offset binary coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT‐based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by application specific integrated circuit (ASIC)‐based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, area‐delay product (ADP), and power delay product (PDP) are evaluated and compared with state‐of‐the‐art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC‐DA‐based filter architecture than the conventional DA‐based filter architecture, respectively.

Implementation of Fir Filter Using Distributed Arithmetic and Distributed Arithmetic Off-Set Binary Coding Algorithms

This paper is the study of implementation of FIR filter using Distributed Arithmetic and Distributed Arithmetic Offset Binary Coding Algorithms. Distributed Arithmetic (DA) had been used to implement an FIR filter due to its high stability and linearity by using look-up table (LUT). The performance of DA technique and DA-OBC for FIR filter design is analyzed and the results are compared to the traditional FIR filter design techniques.

An Efficient FIR Filter Architecture Implementation using Distributed Arithmetic (DA) for DSP Applications

In this paper the proposed efficient FIR filter architecture using a distributed arithmetic (DA) algorithm in which two issues are discussed in the conventional FIR filter. The FIR filter is well known to include delay elements, multipliers and adders. Due to the need for multipliers, this results in 2 demerits which are (i) increased in area and (ii) delayed increases that eventually lead to low efficiency (low speed). A notable feature of the proposed technique is to substitute a trivial amount of indexed LUT pages instead of conventional LUT based DA that it helps to maintain the access time lower. Also, significant idea connected with the proposed technique is required page can be thoroughly selected with the selection module without needing adders that result in reduced computation time. Furthermore, the proposed fast FIR filter is used for the powerful ECG noise elimination technique, which is prevalently used in biomedical and healthcare applications. The designs are simulated and synthesized by using Xilinx ISE. It can be seen from reports that our proposed DA consumes 30% less power for 11-tap FIR filters with a 40% shorter area, while the saving in power consumption for 8-tap FIR filters is 30% to 80% and 35% to 80% in the area. Especially in contrast with all the above-mentioned DA techniques, our enhanced quick FIR filters require less area and less power intake due to their lower memory requirements. All architectures are designed for FIR filters with 4 and 8 taps.

ANALYSIS OF EFFECTS OF USING 9/7 WAVELET COEFFICIENTS IN MULTI-RESOLUTION ANALYSIS

Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.

Design and Implementation of Low-Power, Area-Efficient Fir Filter using Different Distributed Arithmetic Techniques

Background: Distributed Arithmetic (DA) technique is a bit serial operation used to perform vector to vector multiplication in convolution, which is an essential operation in digital filters. This paper presents realization of Finite Impulse Response (FIR) filters using six different DA techniques namely conventional DA, Modified DA (MDA), Offset Binary Coding DA (OBC-DA), Offset Binary Coding Modified DA (OBC-MDA) and LUT-Less DA. Methods: A novel DA method is also introduced which is a combination of multiplexers and Look-Up-Tables (LUT). In DA based FIR filter architecture the partial products of the FIR filter coefficients are pre-calculated and stored in LUTs. The filtering operation is done by shift-accumulation unit. Findings: The designs are simulated using Xilinx ISE and synthesized in Cadence RC using 180-nm technology library. From synthesis reports, it is found that for 4-tap FIR filter, Modified DA consumes 30% less power and 40% less area, whereas for 8-tap FIR filter the saving in power consumption is 30-80% and 35-80% in area. Conclusion: Compared to all the DA techniques mentioned, MDA requires least area and least power consumption because of its less memory requirement. All architectures are designed for 4-tap and 8-tap FIR filters.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field ProgrammableGate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functionssuch as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present amethod for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) andDistributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements areused. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter dueto its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performanceof the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field Programmable Gate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functions such as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present a method for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) and Distributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements are used. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Low Power and Area Efficient 2-D DWT Using 9/7 Filter based on NEDA Technique

In this paper, based on word-serial pipeline architecture, a new efficient distributed arithmetic (NEDA) technique is introduced. This architecture increases the speed and reduced the time of 2-D discrete wavelet transform (DWT). In this design, word-serial pipeline architecture able to compute a complete 2-D discrete wavelet transforms (DWT) binary tree in an on-line fashion, and easily configurable in order to compute any required 2-D DWT sub tree is proposed. In this architecture, free of ROM, multiplication and subtraction, 9 high-pass and 7 low-pass NEDA techniques are used concurrently. The proposed NEDA architecture is 30% faster than compare the exiting architecture and 27% reduced the area. The word-serial pipelines architecture has 100% hardware utilization efficiency.

High Speed and Time Efficient 1-D DWT on Xilinx Virtex4 DWT Using 9/7 Filter Based NEDA Technique

In this paper, we describe an efficient Xilinx Virtix4 discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. This technique supports any size of image pixel value and any level of decomposition. The bit-parallel structure has 100% hardware utilization efficiency. Compared with the existing multiplier-less structures, the proposed structures offer significantly higher throughput rate and involve less area-delay product.

Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic

Distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this brief, two novel DA-based implementation schemes are proposed for adaptive finite-impulse response filters. Different from conventional DA techniques, our proposed schemes use coefficients as addresses to access a series of lookup tables (LUTs) storing sums of delayed and scaled input samples. Two smart LUT updating methods are developed, and least-mean-square adaptation is performed to update the weights and minimize the mean square error between the estimated and desired output. Results show that our two high-performance designs achieve high speed, low computation complexities, and low area cost.

Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm

This paper describes the implementation of highly efficient multiplierless serial and parallel distributed arithmetic algorithm for FIR filters. Distributed Arithmetic (DA) had been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the bitserial and bit-parallel DA technique for FIR filter design is analyzed and the results are compared to the conventional FIR filter design techniques. The proposed algorithm has been synthesized with Xilinx ISE 10.1i and implemented as a target device of Spartan3E FPGA.

A New DA Implementation Technique for Digital Filters Using Radix-16 Modified Booth Algorithm

In this paper, a new DA (Distributed Arithmetic) filter implementation technique is presented. Contrary to the conventional DA technique using ROM, the proposed implementation technique avoids the use of ROM since it does not need the combinations of filter coefficients. Furthermore, by using the Radix-16 modified Booth algorithm, implementation complexity of the proposed structure can be reduced. Through the HDL coding and synthesis, it was shown that 41.6% of implementation area can be reduced.

Configurable Multirate Filter Banks

Multimedia communications require efficient and real-time implementations of multirate digital signal processing systems. The backbone structures of multirate systems are digital multirate filter banks. Therefore, efficient multimedia communications rely, in the first place, on real-time implementations of multirate filter banks. In this paper, we describe a Field Programmable Gate Array (FPGA) implementation of the analysis and synthesis filter banks which are the fundamental components of multirate systems. The implementation utilizes the parallel form of the distributed arithmetic technique which enables maximum exploitation of the parallelism inherent in the multirate filtering operation. Performance results demonstrate the effectiveness of the implementation and suggest that the FPGA platform is indeed attractive for implementing multirate filter banks.

Area efficient FIR filters for high speed FPGA implementation

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm.

Fast Implementation of forward robot kinematics of position with distributed arithmetic architecture

This paper refers to the fast implementation of the forward kinematic equations of position of robotics manipulators, using a distributed arithmetic-based pipeline architecture. The building blocks of this pipeline architecture are the distributed arithmetic-based circuits that implement the matrix-vector multiplications involved in the calculation of the forward kinematics of position. The matrix-vector multiplications are implemented in the distributed arithmetic technique by using auxiliary binary functions, which are stored in look-up tables. The digit-serial configuration of the proposed implementation is described. The serial and the parallel configurations may result as special extreme cases of the digit-serial configuration.

Fast implementation of robot inverse dynamics with distributed arithmetic via a SIMD architecture

Real-time sophisticated robot control schemes require the online evaluation of the inverse robot dynamics model, a computationally intensive task. Research efforts to create efficient implementations of inverse models belong to the domain of computational robot dynamics. The current trends in this domain postulate that major improvements in computational efficiency can be achieved only in the context of customizing the dynamics formulations for specific robots and organizing the numerical computation. In this context, the objective of this paper is to introduce a novel SIMD parallel architecture based upon the distributed arithmetic technique for the efficient implementation of the general-purpose inverse robot dynamic problem. The approach is embedded in the Lagrangian formulation of robot dynamics with all equations expanded symbolically in their scalar form. In the proposed architecture any inherent parallelism of the computations is exploited to partition the inverse dynamics problem into discrete subtasks. The efficiency of the procedure is illustrated via the positioning system of the Puma robot.

Fast implementation of the forward positional acceleration of robots via the distributed arithmetic technique

This paper refers to the fast implementation of the positional forward acceleration of the end effector of revolute robotic arms with spherical wrists, using the distributed arithmetic technique. The acceleration of the end effector is calculated by a cascade configuration of two pipelined arrays that calculate the Jacobian matrix and its time derivative, as well as the centrifugal-Coriolis and linear accelerations. These partial accelerations are then added in the adder tree. The building blocks of the arrays are the distributed arithmetic-based circuits that implement the matrix-vector multiplications involved in the calculations. The digit-serial configuration of the proposed implementation of the positional forward acceleration of the end effector is described. The serial and the parallel configurations may result as special cases of the digit-serial configuration. The proposed distributed arithmetic (DA) implementation of the positional forward acceleration may be applied, after appropriate modifications, to the general case of robots having either revolute or prismatic joints, with any type of wrist.