Output Current Distortion Research Articles

Switching-Cell Four-Leg Current Source Inverter

Conventional current source inverter (CSI) suffers from open-circuit problem during switch transition. Thus, overlap-time should be inserted in the gate signals for safe commutation. The overlap-time distorts output current waveforms and increases total harmonic distortion of output current. Moreover, it reduces the current source utilization of the inverter. To solve these problems, this article proposes a new three-phase four-leg switching-cell (SC) CSI, abbreviated as H8-SC-CSI. With the help of the SC structure, the reliability of the proposed inverter is greatly enhanced as open-circuit concerns are eliminated. In addition, with the intrinsic voltage clamping action of the SC structure, switch voltage overshoot at turn-off is mitigated. In the proposed CSI, the switch overlap-time can be minimized or eliminated because the inductor current can flow through the SC capacitors. A 1.2 kW prototype inverter is designed and tested to verify the feasibility of the circuit.

Device-Level Loss Balancing Control for Modular Multilevel Converters

Modular multilevel converter (MMC) is a promising topology in medium/high-voltage applications for its merits, e.g., scalability, low output current total harmonic distortion, and high efficiency. But the reliability of MMCs is questionable due to more semiconductor devices used than other topologies. Another reliability problem of MMC is the significant uneven loss distribution between the top and bottom semiconductor devices within one submodule (SM) owing to the dc component in the arm currents. The stress difference caused by the uneven loss distribution between the top and bottom semiconductor modules will lead to the lifetime difference of the semiconductor devices, which shortens the lifetime of the whole MMC system. To extend the lifetime of MMCs without the modification of system hardware, this article proposes a device-level loss balancing control method. In this method, the accurate device loss models are established to feedback real-time device losses into the loss balancing controller. The controller (by regulating the SM capacitor voltages) adjusts the semiconductor conducting duty cycles to even the loss distribution without affecting the performance of the ac output and capacitor-voltage balancing. The effectiveness of the proposed control method is validated through experimental results.

Carrier phase shift modulation and voltage equalization control strategy in modular multilevel converter

In order to solve the problem of voltage fluctuation of sub-module capacitors in Modular Multilevel Converter, based on carrier phase-shifted sinusoidal pulse width modulations, this paper analyzes the effect of different carrier phase shift modulation and the number of sub-modules on a single bridge arm on the number of output levels and uses proportional control to make capacitor voltage balance and PI control to suppress bridge arm circulation. The method has a good stability effect on the sub-module capacitor voltage.A 31-level model is built in MATLAB/simulink to analyze the capacitor voltage fluctuation, output current and voltage distortion rate, and bridge arm current of the sub-module. The voltage and circulation fluctuation range is compared when there is no circulation suppression. It is verified that the method is simple and effective.

Increasing the Utilization Factor of an Autonomous Inverter under Space Vector Control

Control systems for ac electric drive frequency converters are based on pulse width modulation (PWM) algorithms. Their use leads to problems: significant output voltage and current distortion, the appearance of shaft torque pulsation and its rotation frequency, and, as a result, an increase in vibrations and noise of the drive motor. Semiconductor PMW converters are also characterized by underutilized voltage. The solution to these problems is possible through applying space vector modulation (SVM) algorithms, however the voltage efficiency remains at the PWM level. To solve these problems, it is reasonable to use modified SVM algorithms that will provide semiconductor converter operation in the overmodulation mode. This article considers the development of overmodulation algorithms, the application of which will solve these problems. The following developed algorithms for the overmodulation of spatial vector control systems are presented: an alternating active overmodulation algorithm, adaptive overmodulation algorithm, and synchronous overmodulation algorithm. Their mathematical formulation is given. It is shown that overmodulation algorithms provide an increased voltage utilization factor of the autonomous inverter. When using the developed overmodulation algorithms, the output current of the autonomous inverter has a quasi-sinusoidal shape. The minimum autonomous inverter output current distortion coefficient is provided when using the synchronous overmodulation algorithm at a level of no more than 10%. The switching frequency of the autonomous inverter becomes lower, which leads to reduced switching losses. It is shown that the use of overmodulation algorithms is feasible and provides higher values of such indicators of electric energy conversion efficiency as: output current and voltage distortion coefficients, voltage utilization factor of the autonomous inverter, amplitude of the fundamental harmonic at the same value of the space vector modulation period and switching frequency.

Minimum Cell Operation Control for Power Loss Reduction in MMC-Based STATCOM

This article proposes a minimum cell operation control to reduce power losses in static synchronous compensator (STATCOM) based on the modular multilevel converter (MMC). The main principle is to bypass cells from the MMC, according to the reactive power reference. For such, analytical expressions for the minimum dc-link voltage to keep the converter operation in the modulator linear region are derived. These expressions are used to compute the number of cells, which can be bypassed for given operation conditions. Moreover, a simplified analytical modeling of conduction losses in MMC is presented. The limits of the proposed strategy are also investigated. Simulation studies are performed during cell bypass conditions to analyze its impact on the converter dynamics. In addition, the output current distortion and power losses under different operating conditions are evaluated. Finally, a one-year energy-saving study was conducted for a real reactive power profile, which presented a 7.37% reduction in the yearly energy losses. The results indicated that this methodology is a breakthrough solution to reduce power losses and operational costs. The proposed technique can be applied in MMC-based STATCOMs with more than ten cells per arm and does not require additional hardware.

Cascaded Multilevel PV Inverter With Improved Harmonic Performance During Power Imbalance Between Power Cells

The difference in power cell irradiances in cascaded multilevel converters results in different duty cycles among those cells when maintaining the maximum power point tracking (MPPT). However, the difference in cell duty cycles is undesired since it is proportional to the output voltage and current distortions. To this regard, a multilevel topology for photovoltaic (PV) applications is proposed, where an H6 bridge power cell is used instead of an H-bridge one. In case of solar irradiance mismatch among the power cells, the proposed converter injects power with lower voltage from the shaded cells without altering the PV voltage; hence maintaining the MPPT operation. This modification allows us to retain an equal duty cycle in all the power cells whatever the meteorological conditions are present; consequently, maintaining good output voltage and current waveform qualities. To test the effectiveness of the proposed solution, a detailed simulation model as well as an experimental prototype is built. The obtained results show that the proposed topology provides significantly improved output voltage and current qualities compared to the cascaded H-bridge one. The performance of the proposed topology compared to one offering improved harmonics performance, according to the European efficiency, has been also compared, where an enhancement of 2.64% has been registered.

Control of Grid-Following Inverters Under Unbalanced Grid Conditions

This paper proposes a new control scheme to eliminate the 3rd harmonic in the output currents of grid-following inverters under unbalanced grid conditions. Unbalanced grids adversely affect the performance of grid-following inverters due to the oscillations appearing on the DC-link voltage with a frequency twice the line frequency. The paper is based on instantaneous active reactive control (IARC) technique due to its advantages over other existing methods. However, the presence of severe asymmetrical 3rd harmonic distortions in the inverter output currents is the main challenge with IARC method, which impairs the power quality requirements. This paper enhances the IARC scheme by proposing a 3rd harmonic elimination approach by adopting a current reference generation method using the symmetric sequence components concept. Furthermore, the proposed scheme complies with the grid code requirements by injecting the requested reactive current. Finally, the proposed approach is evaluated by theoretical and simulation analysis and validated experimentally using a hardware setup.

DC-link loop bandwidth selection strategy for grid-connected inverters considering power quality requirements

DC-link voltage and output current control loops are two cascaded loops in the control structure of grid-connected inverters. A high DC-link voltage loop bandwidth (DCL-BW) provides more disturbance rejection capability for the control loop and is preferred from control system perspective. However, for stability issues, this BW is limited and must be sufficiently less than that of the current control loop. Among the different control schemes, instantaneous active reactive control (IARC) method provides the highest possible DCL-BW (i.e., 0.02 × switching frequency). Having this degree of freedom in the controller design, a proper methodology should be defined for selection of DCL-BW. In this paper, different factors including the output current harmonic distortion, low-order harmonics on DC link voltage, and the inverter nominal rating are introduced as affecting parameters for DCL-BW selection. Accordingly, a DCL-BW selection strategy based on output current harmonic distortion is proposed. The proposed method enhances the power quality indices of the grid-connected inverters, which especially is useful for few kVA power inverters. Finally, to validate the conducted analysis, experimental and simulation results are provided.

Controller for the Grid-Connected Microinverter Output Current Tracking

The modification of the proportional–integral (PI) controller with the variable proportional constant for tracking of the grid-connected photovoltaic microinverter output current has been proposed. The obtained results show that in the case when the proportional constant of the PI controller varies in time according to the appropriate law, the microinverter output current sinus shape distortions decrease as compared to the case when the ordinary PI controller is used. The operation of the microinverter with the proposed controller was investigated for the cases when the electrical grid voltage sinus shape is not distorted and when it is distorted by the higher harmonics.

Overlap‐time compensation technique for current‐source power inverter

A current source type power inverter is an inverter converting the dc current source to be ac current with magnitude, frequency and phase angle can be controlled. In a voltage source inverter, a short circuit condition is prohibited, because an excessive current may destroy the inverter circuits. In contrast, because inductors are used as energy buffer, an open circuit must be avoided in the operation of a current source inverter. In order to operate inverter properly, overlap-time is attached in the firing signals of power switches to avoid open circuit condition. However, adding overlap-time will generate distortion of the ac output current. Hence, compensation of overlap-time is absolutely needed for current source inverter to output high quality current waveform. A new overlap-time compensation method for current source inverter is proposed in this paper. The method utilized triangular carriers and sinusoidal signal for modulation strategy to generate gating signals of inverter with overlap-time compensation capability. The new method was examined using computer simulations. Further, experimental tests of inverter circuits applying overlap-time compensation method were also presented and discussed. The test results verified that the proposed method worked well suppressing distortions and harmonics of the ac current waveform caused by the overlap-time.

Fault Detection Method Using a Convolution Neural Network for Hybrid Active Neutral-Point Clamped Inverters

This article presents an open-switch fault detection method for a hybrid active neutral-point clamped (HANPC) inverter based on deep learning technology. The HANPC inverter generates a three-level output voltage with four silicon switches and two silicon carbide switches per phase. The probability of open fault in switching devices increases because of the large number of switches of the entire power converter. The open-switch fault causes distortion of output currents. A convolution neural network (CNN) comprising several convolution layers and fully connected layers is used to extract features of distorted currents. A CNN network was trained using three-phase current information to determine the location of the open-switch fault. Our proposed CNN model can accurately detect approximately 99.6% of open-switch faults without requiring additional circuitry and regardless of the current level within an average time of 1.027ms. The feasibility and effectiveness of the proposed method are verified by experimental results.

Advanced Variable Switching Frequency Control for Improving Weighted Efficiency of Distributed Renewable Generation Systems

Energy conversion efficiency and output current harmonic distortion are two key performance measures of small-scale grid-connected distributed generation (DG) systems. As the interface between renewable energy generators and the utility grid, dc-ac converters (i.e. inverters) have been increasingly used in recent years. In this paper, a novel control algorithm termed “variable switching frequency control (VSFC)” is proposed to increase the weighted efficiency of the inverter for renewable energy generators through selection of optimal switching frequencies of pulse width modulation (PWM) in real time, based on estimation of output current harmonic distortion. Both simulation and experimental results indicate the proposed VSFC algorithm ensures that the inverter can operate with maximum efficiencies at different output levels while satisfying standard requirements for grid current harmonic distortion. Furthermore, implementation of this method to improve the inverter efficiency has no impact on inverter costs or control complexity.

Compact Three Phase Multilevel Inverter for Low and Medium Power Photovoltaic Systems

A new three phase multilevel inverter with reduced number of components count is proposed in this paper. This inverter is designed using a single DC source per phase to generate multiple level output voltage which makes it suitable for low and medium voltage applications, including ac-coupled renewables or energy storages. A generalized circuit configuration is shown in this paper following which the number of output voltage level can be increased as per expectation. Although, each element endures the voltage stress equivalent to the input DC voltage, the value of total standing voltage (TSV) is reduced by the utilization of minimized number of components with respect to the number of series connected capacitors. Further, staircase modulation scheme is used to generate the switching signals. Hence, the proposed inverter can be operated at low switching frequency with optimal output current harmonic distortion which decreases switching losses and suppresses power factor falling. In order to validate the theoretical explanations and practical performances of the proposed inverter, the hypothesis is simulated for 9, 13 and 39 output voltage level inverters for three phase with a line voltage total harmonic distortion (THD) of 6.06%, 4.16% and 2.10% respectively in MATLAB/Simulink and a 5-level single phase laboratory prototype is implemented in the laboratory.

Simplified Space-Vector Modulation Strategy for Indirect Matrix Converter With Common-Mode Voltage and Harmonic Distortion Reduction

This paper presents a simple space vector modulation (SVM) strategy for a three-phase indirect matrix converter (IMC) to reduce common-mode voltage (CMV) and output harmonic distortion. To suppress the CMV peak value to 57.7% of the input phase voltage, three active voltage vectors are used to generate the desired output voltage with arbitrary amplitude and frequency. However, the output waveform quality of the IMC deteriorates due to the absence of zero voltage vectors. To overcome this problem, this paper proposes to redesign control of the rectifier stage by utilizing three active current vectors instead of two, as is common. Consequently, a constant average DC-link voltage is achieved, which can improve the output performance in terms of output voltage and current harmonic distortion. Compared to the existing strategies, the proposed strategy can reduce the CMV and maintain output harmonic distortion without increasing the computation burden. Implementation of the proposed strategy is also straightforward and simple. Simulated and experimental results are provided to verify the effectiveness of the proposed strategy.

A Novel Low Common-Mode Voltage Modulation Strategy for ANPC-5L Inverter

In order to suppress the leakage current of the active neutral point clamed five-level (ANPC-5L) inverter, this paper proposes a novel low common-mode voltage (CMV) modulation strategy based on the space vector modulation thought. Only the 55 voltage vectors with low CMV amplitude instead of all 125 voltage vectors are utilized. The CMV amplitude is suppressed to one-twelfth of the DC bus voltage (Vdc). In the simplified five-level space vector diagram, “obtuse triangle” synthesis principle is used to control the CMV changes twice in each carrier cycle, and get lower output current total harmonic distortion (THD). According to the vector thought, a carrier implementation method based on zero sequence voltage injection and carrier splitting is proposed. This method simplifies the calculation and is easy to implement.Simulation results prove the correctness and feasibility of this low CMV modulation strategy.

Resistorless Realization of First‐Order Current Mode Universal Filter

AbstractThis paper proposes a first‐order current mode universal filter employing single active building block, namely differential difference dual‐X second generation current conveyor. The proposed filter is designed to provide multiple filter responses simultaneously, namely low‐pass, high‐pass, and all‐pass on applying a current signal at its input terminal. The proposed work also enjoys the presence of metal oxide semiconductor transistors working as tunable resistors. Some of the key features of the proposed filter are as follows: use of single passive element (a grounded capacitor), ease of cascadability as all the outputs are available at highimpedance ports, low active and passive sensitivities, significantly high frequency of operation (3 MHz), low total harmonic distortion of output current (1.28%), low output current noise (10 pA/√Hz), and low power dissipation (2 mW). A detailed study of device nonidealities is also presented to show the satisfactory performance of the proposed structure under all practical considerations. PSPICE simulations effectively demonstrate the good performance of the proposed filter.

Open Fault Diagnosis and Tolerance Control for Grid-Connected Hybrid Active Neutral-Point- Clamped Inverters With Optimized Carrier-Based Pulse Width Modulation

This paper proposes open fault diagnosis and tolerance control methods for grid-connected hybrid active neutral-point-clamped (ANPC) inverters with optimized carrier-based pulse width modulation. The hybrid ANPC inverter is composed of silicon carbide metal-oxide-semiconductor field effect transistors and Si-insulated gate bipolar transistors. Open faults of switch devices lead to the distortion of output currents, inverter performance degradation, and low reliability. Therefore, the open-circuit fault diagnosis and the tolerance control methods should be handled to improve the reliability of the inverter. The fault tolerance control methods for grid-connected inverters should also consider the fixed voltage modulation index as the modulation index is fixed. In this study, the proposed fault tolerance control method handles the open fault without reducing the modulation index. The implementation of the proposed method is easy and can be conducted through a simple change in the reference waveform. The effectiveness of the proposed fault detection and fault tolerance control methods was verified through the simulation and experimental results.

Common-Mode Resonance Damping and DC Voltage Balancing Strategy for LCCL-Filtered Three-Level Photovoltaic Grid-Tied Inverters

The leakage current caused by common-mode (CM) voltage is a critical issue in transformerless three-level photovoltaic (PV) inverters, which can increase the output current distortion, bring extra power losses, aggravate the electromagnetic interference, and even cause degradation of the panels and safety issues. The LCCL filter was proven to be effective to mitigate the leakage current, whose capacitor is split into two parts, and the common point of the smaller one is connected to the neutral-point (NP) of the DC-link. However, the LCCL-filtered three-level inverter suffers from the CM resonance of the neutral current and the NP voltage imbalance. Therefore, this paper proposes a CM resonance damping and NP voltage balancing strategy for the transformerless LCCL-filtered three-level PV inverter. A novel dual-cascade-loop with a dc voltage-difference outer-loop and a neutral-current inner-loop is proposed to control the CM voltage with a αβγ-frame space vector pulse width modulation (SVPWM) for damping the CM resonance and balancing the NP voltage. At last, the effectiveness of the proposed strategy is experimentally validated through a 10 kW transformerless LCCL-filtered T-type three-level PV inverter.

The Effect of Using Filter on Total Harmonic Distortion in Multilevel Inverter

Multi-level inverter used in applications that require high power. The important factor in multi-level inverter is Total Harmonic Distortion (THD). This study discuss nine level cascaded H-bridge multilevel inverter. Also, proposed the effects of using filter on waveform and Total Harmonic Distortion (THD) of output voltage and current. Discussed LC low pass filter and sinusoidal pulse width modulation as control technique of switches. Comparison THD of nine level cascaded H-bridge multilevel inverter with and without filter. The proposed level and filter are design and simulate by MATLAB 2010 Version 7.11.0. The simulation results show the effects of using filter on THD and waveform of output voltage and current. Different methods for choosing filter value are used to illustrate the filter effect.

An Enhanced Model Predictive Control Using Virtual Space Vectors for Grid-Connected Three-Level Neutral-Point Clamped Inverters

Reliability of power systems can be improved by the use of voltage source inverters (VSIs) with fast dynamic control, which can handle uncertainties induced by renewable energy resources and nonlinear loads. To ensure fast-dynamic response and simplified controller design, various model predictive control (MPC) methods are investigated in this paper. In the conventional MPC design for three-level VSIs, the cost function requires an additional term to ensure the balance of the neutral-point voltage (NP-V), which however can considerably impact the main goal of the MPC. To address this issue, an enhanced MPC using virtual space vectors is proposed, which allows the use of a significantly reduced weighting factor for the term in the cost function for NP-V balancing, while retaining fast-dynamic response. Additionally, the proposed MPC leads to reduced harmonic distortion in the VSI output voltage and current. Both simulation and controller hardware-in-the-loop studies are performed to demonstrate the effectiveness of the proposed enhanced MPC in an operating microgrid under both steady-state and fast-transient conditions.