Discrete Wavelet Transform Structure Research Articles

Optimizing Visual Sensor Node Image Compression for Resource-Constrained Environments

Abstract: An Approximate hybrid multiplier design is proposed to reduce the data-path width of lifting 2-D discrete wavelet transform (DWT) especially for wireless visual sensor node applications. The proposed multiplier design takes multiplier operand of size less by 3 bit and calculates full-width outputs with marginal loss of accuracy, which is significant. The proposed approximate 2-D DWT structure uses data-path DWT levels and produces reconstructed color images higher than the 70-dB peak-signal-to-noise ratio (PSNR). Compared with the existing fractional wavelet transform (FrWT)-based 2D DWT structures, the proposed structure has a smaller data-path width and free from overhead. Compared with the existing parallel structure

Approximate Lifting 2-D DWT Hardware Design for Image Encoder of Wireless Visual Sensors

In this paper, a novel approximate hybrid multiplier design is proposed to reduce the data-path width of lifting two-dimensional (2-D) discrete wavelet transform (DWT) especially for wireless visual sensor node applications. The proposed multiplier design takes multiplier operand of size less by 3-bit and calculates full-width outputs with marginal loss of accuracy which is significant. A parallel approximate lifting 2-D DWT structure is derived using the proposed multiplier design. The proposed approximate 2-D DWT structure uses data-path width 9 and 11 for first and second DWT levels and produces reconstructed colour images higher than 70dB peak-signal-to-noise ratio (PSNR). Compared with the existing fractional wavelet transform (FrWT)-based 2-D DWT structures, the proposed structure has a smaller data-path width and free from overhead. The proposed structure has equal or marginally higher on-chip memory requirement than the existing FrWT based 2-D DWT structures, but involves a substantially less area-delay product (ADP) and energy per image (EPI). The ADP and EPI reduction is O(10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ×). Compared with the existing parallel structure based on hybrid approximate radix-4 and radix-8 encoded Booth multiplier, the proposed approximate structure involves nearly 23% less ADP and 22% less EPI and calculates output images with nearly (4 ~ 7)dB higher PSNR.

Computational methods to increase the speed of FPGA-based discrete wavelet transforms

The article considers the computational methods and features of the construction of a complex functional block for the implementation of the discrete wavelet transform (DWT) Dobeshie 9/7 in digital image signal processing systems based on FPGA. We proposed a mathematical model and algorithms for the implementation of parallel and series-convector methods of signal processing to calculate the coefficients of a discrete bi-orthogonal Dobeshie wavelet 9/7 taking into account the architecture of used FPGA. The model is based on wavelet transform factorization methods using lifting schemes. In contrast to conventional lifting schemes, the proposed method and algorithms can increase the speed of FPGA calculations with simplified hardware implementation. CAD Quartus II and ModelSim are used as a development environment. The behavioral model is written in Verilog HDL. Altera Cyclone® IV 4CE115 was used as FPGA. On the basis of the obtained behavioral model the testing module was developed and the simulation of digital circuit in the ModelSim environment was carried out. The formula for estimating the number of clock cycles of the forward and reverse DWT has been proposed; on its basis the estimate of the number of parallel computations depending on the number of input elements and the characteristics of the FPGA was obtained. As a result of experiments the dependences of the number of cycles for DWT computation depending on the size of the side of a square image with different variants of the number of parallel processing blocks were obtained. It is shown that parallel work of several independent modules gives a possibility to conduct concurrent processing of several input columns (rows) from input 2D array, and unification of the multiplier-summing module allows to increase efficiency of calculations and to reduce volume of occupied hardware resources. Conveyor based DWT structure is characterized by less hardware costs in terms of implementation of the calculator unit and memory allocation. As a result of testing the digital circuit, it was found that the developed block structure can significantly increase the DWT speed as well as reduce the cost of the system on a chip. The proposed realization of the block of two-dimensional forward and reverse wavelet transform for the Dobeshi 9/7 filter bank forms a complete module and can be used as a ready-made complex functional block for further development of high quality image transmission systems in real time.

Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm

An efficient architecture of discrete wavelet transform (DWT) in two-dimension (2D) is presented in this paper. The proposed structure has a higher hardware efficiency and better performance than the other DWT structures. The conventional lifting scheme is modified to reduce the latency and critical path to one multiplier delay (1Tm). The processing speed of the architecture is increased by introducing four pipeline stages in the DWT structure. Cohen-Daubechies-Feauveau (CDF) 9/7 wavelet filter is implemented in the paper. The data scanning of the input image for processing is done in Z-fashion. The computation time of an N × N image is N2/2 and the temporal buffer requirement is 4N. The DWT architecture developed based on the modified lifting scheme has a regular data flow with a throughput rate of two. Very high speed hardware description language (VHDL) is used to describe the digital design. The architecture is implemented on CADENCE tool with CMOS 180 nm technology. The results after comparison indicate that the proposed architecture is hardware efficient and memory utilisation is reasonable as a result of which this structure can be used in real-time image and video compression.

An Efficient Architecture for Modified Lifting-Based Discrete Wavelet Transform

A high speed and memory efficient lifting based architecture for one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is proposed in this paper. The lifting algorithm is modified in this work to achieve a critical path of one multiplier delay with minimum pipeline registers. A 1-D DWT structure with two-input/two-output and four-input/four-output is developed based on the modified lifting scheme. The proposed 2-D DWT architecture for the Daubechies 5/3 and 9/7 filter comprises of two 1-D processors, together with a transpose and a temporal memory. An efficient transpose block is presented, which utilizes three registers to transpose the output sequence of the 1-D DWT block. The transpose block is independent of the size of the image read for the transform. The scanning process of an $$N \times N$$ image for a one-level 2-D transform is in Z fashion to minimize the temporal buffer to 4N and 2N for the 9/7 and 5/3 mode DWT respectively. The comparison results show that the proposed structure is hardware cost-effective and memory efficient, which is favorable for real-time visual operations. The model is described in VHDL and synthesized using the Cadence tool in 90 nm technology.

A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell

In this paper, area and power efficient lifting and flipping discrete wavelet transform (DWT) architectures are proposed. DWT architectural metrics such as critical path delay, area of utilization, power consumption are mainly dependent on the arithmetic components such as adders and multipliers. They constitute the data-path of the DWT structure. A multiplier of the DWT data-path plays major role in basic lifting, flipping cells and further it demands optimization. In this work, an area and power efficient lifting and flipping cells are implemented using look up table (LUT) based multipliers. The proposed DWT architectures are implemented in gate level Verilog HDL and are synthesized using Cadence RC design compiler. Based on the area, delay, and power results obtained from post synthesis, parameters like area delay product (ADP) and power delay product (PDP) are computed. The ADP and PDP values prove that the proposed LUT based architectures are efficient over recently projected lifting and flipping DWT architectures.

Power-optimized log-based image processing system

The continuous development of devices such as mobile phones and digital cameras has led to a higher amount of research being dedicated to the image processing field. Today's image-acquiring tools require battery-operated power, and hence, power optimization becomes a major factor to be considered in the hardware implementation of image systems. This paper proposes an image processing system which utilizes set partitioning in hierarchical trees (SPIHT)-integrated discrete wavelet transform (DWT) structure for image processing. The overall advantage of this proposal is achieved by modifying the arithmetic units in the DWT structure. Utilizing a logarithm-based floating point unit (FPU) in the DWT computation structures, the logarithmic number system (LNS) adaptation in the arithmetic unit results in overall accuracy enhancement with reduced area and power consumption. To ensure the versatility of the proposal and for further evaluating the performance and correctness of the structure, the model is implemented using Xilinx and Altera field-programmable gate array (FPGA) devices. The analyses obtained from the implementation show that the structure incorporated with the log-based FPU is 25% more accurate with 47% reduced power consumption than the integer-styled FPU incorporated DWTs, along with enhanced speed and optimal area utilization.

A Multiplier-Less Lifting Scheme Based DWT Structure

The merits of Discrete Wavelet Transform (DWT) over other traditional transforms have led to tremendous focus on the applications of Wavelet Transforms. This leads to the requirement for developing a hardware efficient VLSI implementation of the DWT along with low power consumption. In this paper, DWT architecture based on lifting scheme is considered with suitable modifications to the architecture by adopting low power techniques, which contributes to hardware efficient and low power implementation. A shift-add multiplier with signed floating point consideration is used to construct a 2D-DWT lifting based architecture. This proposed multiplier eliminates the use of power consuming costly conventional multipliers. The proposed multiplier represents the signed floating point results which is the drawback of representation in Verilog implementation .A Verilog model is designed and synthesized for the proposed architecture. The synthesis results indicate that Xilinx vertix-4 FPGA implementation of the proposed technique is demonstrated which achieves Multiplier less structure, 12% reduced number of slices and 10% reduced power architecture compared with conventional one level lifting 2D-DWT architecture using 9/7 Filter