Discrete Cosine Transform Algorithm Research Articles

Integer fast lapped transforms based on direct-lifting of DCTs for lossy-to-lossless image coding

The discrete cosine transforms (DCTs) have found wide applications in image/video compression (image coding). DCT-based lapped transforms (LTs), called fast LTs (FLTs), overcome blocking artifacts generated at low bit rate image coding by DCT while keeping fast implementation. This paper presents a realization of more effective integer FLT (IntFLT) for lossy-to-lossless image coding, which is unified lossless and lossy image coding, than the conventional IntFLTs. It is composed of few operations and direct application of DCTs to lifting blocks, called direct-lifting of DCTs. Since the direct-lifting can reuse any existing software/hardware for DCTs, the proposed IntFLTs have a great potential for fast implementation which is dependent on the architecture design and DCT algorithms. Furthermore, the proposed IntFLTs do not need any side information unlike integer DCT (IntDCT) based on direct-lifting as our previous work. Moreover, they can be easily extended to larger size which is recently required as in DCT for the standard H.26x series. As a result, the proposed method shows better lossy-to-lossless image coding than the conventional IntFLTs.

A Single-Channel Architecture for Algebraic Integer-Based 8$\,\times\,$8 2-D DCT Computation

An area efficient row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) for image and video processing. The proposed architecture computes 8 × 8 2-D DCT transform based on the Arai DCT algorithm. An improved fast algorithm for AI-based 1-D DCT computation is proposed along with a single channel 2-D DCT architecture. The design improves on the four-channel AI DCT architecture that was published recently by reducing the number of integer channels to one and the number of eight-point 1-D DCT cores from five down to two. The architecture offers exact computation of 8 × 8 blocks of the 2-D DCT coefficients up to the FRS, which converts the coefficients from the AI representation to fixed-point format using the method of expansion factors. Prototype circuits corresponding to FRS blocks based on two expansion factors are realized, tested, and verified on FPGA-chip, using a Xilinx Virtex-6 XC6VLX240T device. Post place-and-route results show a 20% reduction in terms of area compared to the 2-D DCT architecture requiring five 1-D AI cores. The area-time and area-time <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> complexity metrics are also reduced by 23% and 22% respectively for designs with eight-bit input word length. The digital realizations are simulated up to place and route for ASICs using 45 nm CMOS standard cells. The maximum estimated clock rate is 951 MHz for the CMOS realizations indicating 7.608·10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> pixels/s and a 8 × 8 block rate of 118.875 MHz.

A Novel Autofocus Algorithm Based on DCT Criteria for SAR Images

A novel autofocus algorithm based on Discrete Cosine Transform (DCT) for Synthetic Aperture Radar (SAR) images is presented in this paper. The method, which starts with complex phase-degraded SAR images, with the phase errors model is introduced into the range-compressed phase-history domain, carries out phase errors correction by changing the focus until the intensity weight function of the azimuth profile’s DCT coefficients in the area of high sequences is maximized. Compared with Phase Gradient Autofocus (PGA) algorithm, the proposed method does not need to isolate prominent point target in image domain and is especially suitable for the images without specific characteristic. Due to the fact that there are fast algorithms for DCT, this autofocus algorithm is of less computational complexity and easy to implement. The simulation and the processing results of the measured data show the validity of the proposed method.

Analysis of MPC Image Compression using DCT 2 in Matlab

compression is to reduce irrelevance data and redundancy of the image data in order to be able to store or transmit data in an efficient form. Image compression scheme either be in lossy method or lossless method. Lossy algorithms are especially suitable for transmit images across the network with minor (sometimes imperceptible) loss of fidelity of information. In this work, propose MPC (Maximum PSNR using Coefficient) using DCT algorithm for image compression and reconstruction taking benefit from the advantages of DCT algorithms. The algorithm performs the Discrete Cosine Transform (DCT) on the coefficients. The objective of the proposed system to study how the image is compressed using MPC method and discrete cosine transforms to attain maximum PSNR value. To attain maximum PSNR value, using coefficient, the images are analyzed and get compressed image with good quality. Coefficient reads the index of RGB values of given input image and processing that image in iteration manner. Coefficient is the most important factor that affects the image quality. Using Coefficients in Matlab, the images are analyzed and get maximum PSNR value is attained.

Research of Blurred Face Image Detection Based on DCT and Edge Detection Algorithm

Multimedia has been widely used on the mobile platform. Due to its mobility and instability,the mobile terminal inevitably produces some blurred pictures (especially when shooting human faces). Hence, if these blurred and normal images are well classified and separated, it will be significant to improve the browsing efficiency. This paper focuses onresearch of two popular blur detection algorithms, DCT (Discrete Cosine Transform) and edge detection algorithm. It also offers the implementation of the blurred face image detection and classification system based on these two algorithms. At last it contrasts these two algorithms and draws a conclusion.

Video Watermarking Algorithm Based on DCT and SVD

This paper presents an original video based on DCT (Discrete Cosine Transform) and SVD (singular value decomposition) algorithm combined adaptive watermark embedding algorithm. Algorithm will first split the video stream into different scenes, each frame of the discrete cosine transform, and its singular value decomposition of the DC coefficient; the original watermark image and after scrambling algorithm using singular value decomposition singular value sequence, and finally watermarked image. Experiments show that the algorithm meet the invisibility requirements also meet the robustness requirements, efficiently against attacks as frame dropping, Gaussian Noise and Compression attack.

Independently updating the DCT and DST for shifting windowed data

When processing a signal or an image using the Discrete Cosine Transform (DCT) or Discrete Sine Transform (DST), a typical approach is to extract a portion of the signal by windowing and then form the DCT or DST of the window contents. By shifting the window point by point over the signal, the entire signal may be processed. In this paper we develop algorithms to “update” the DCT and DST to reflect the modified window contents using less computation than by directly evaluating the modified transform via standard Fast Transform algorithms. Our algorithms constitute an improvement over previous DCT/ DST update algorithms because our approach establishes independence between the DCT and the DST: the algorithm for DCT makes use only of DCT terms, and similarly for DST. Algorithms are derived for use without windowing and with split-triangular, Hanning, Hamming and Blackman windows.

Zero‐quantised discrete cosine transform coefficients prediction technique for intra‐frame video encoding

One promising solution to reduce the computational complexity of discrete cosine transform (DCT) is to identify the redundant computations and to get rid of them. In this study, the authors present a new method to predict zero-quantised DCT coefficients for efficient implementation of intra-frame video encoding by identifying such redundant computations. Traditional methods use the Gaussian statistical model of residual pixels to predict all-zero or partial-zero blocks. The proposed method is based on two key ideas. At first, the bounds of DCT coefficients are derived from the intermediate signals of the Loeffler DCT algorithm instead of calculating the sum of absolute difference (SAD) of residual pixels. The sufficiency conditions are then suitably chosen to predict the zero-quantised coefficients to reduce the arithmetic complexity without degrading the video quality. Simulation results are found to validate the analytical model and show that the proposed prediction eliminates more redundant computations than the existing methods. Moreover, the authors have derived a pipelined VLSI architecture of the proposed prediction scheme which offers a saving of more than 63 and 91% of multiplications of the second stage of one-dimensional DCT for high and low bit-rate intra-video encoding, respectively.

A digital hardware fast algorithm and FPGA-based prototype for a novel 16-point approximate DCT for image compression applications

The discrete cosine transform (DCT) is the key step in many image and video coding standards. The eight-point DCT is an important special case, possessing several low-complexity approximations widely investigated. However, the 16-point DCT transform has energy compaction advantages. In this sense, this paper presents a new 16-point DCT approximation with null multiplicative complexity. The proposed transform matrix is orthogonal and contains only zeros and ones. The proposed transform outperforms the well-known Walsh–Hadamard transform and the current state-of-the-art 16-point approximation. A fast algorithm for the proposed transform is also introduced. This fast algorithm is experimentally validated using hardware implementations that are physically realized and verified on a 40 nm CMOS Xilinx Virtex-6 XC6VLX240T FPGA chip for a maximum clock rate of 342 MHz. Rapid prototypes on FPGA for a 8-bit input word size show significant improvement in compressed image quality by up to 1–2 dB at the cost of only eight adders compared to the state-of-art 16-point DCT approximation algorithm in the literature (Bouguezel et al 2010 Proc. 53rd IEEE Int. Midwest Symp. on Circuits and Systems).

An algebraic method for synthesizing fast algorithms of discrete cosine transform of arbitrary size

An algebraic method for synthesizing fast algorithms of the discrete cosine transform (DCT) of arbitrary size is proposed. The method is based on the polynomial algebra \(\mathbb{F}{{[x]} \mathord{\left/ {\vphantom {{[x]} {p(x)}}} \right. \kern-\nulldelimiterspace} {p(x)}}\) associated with the DCT. The fast DCT algorithm comes as a result of the step-by-step decomposition of this algebra. In turn, the decomposition requires step-by-step factorization of the polynomial p(x). This problem is solved using Galois’s theory, which allows finding all the subfields of the splitting field of the polynomial p(x) where p(x) can be factorized.

Field programmable gate array (FPGA) realization of a fast 2-D discrete cosine transform algorithm for higher image compression

This paper describes the field programmable gate array (FPGA) implementation of a fast 2-D discrete cosine transform (DCT) chip for higher image compression ratio. The development of encoding and decoding parts of 2-D DCT algorithm is carried out by using Matlab simulation tools and VHSIC hardware descriptive language (VHDL). Comparisons of results for higher image compression ratio as obtained by using Matlab are presented. To improve a fast processor, we have also enhanced the functionality of the arithmetic logic unit (ALU) block in the DCT chip in order to design a fast 2-D DCT chip. The developed VHDL code of the 2-D DCT algorithm is incorporated with the VHDL codes of the enhanced ALU block. The synthesis software, Quartus-II integrated synthesis (QIS) from Altera has been used to obtain hardware blocks for the fast 2-D DCT processor. Performance evaluation of the 2-D DCT processor was achieved using Altera digital library from FPGA technology (TSMC 90 nm). The evaluated parameters are given such as maximum clock frequency of 140 MHz, total power dissipation of 638.84 mW and number of adaptive logic modules (ALMs) as 128. The enhanced 2-D DCT chip is intended for wireless image communication applications. Key words: 2-D discrete cosines transform (DCT), image transforms, VHSIC hardware descriptive language (VHDL), synthesis, field programmable gate array (FPGA).

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy

This paper presents a dynamic bit-width adaptation scheme for applications using discrete cosine transform (DCT). The technique can efficiently trade off image quality and computation energy. Based on sensitivity differences of 64 DCT coefficients, separate operand bit-widths are used for different frequency components to reduce computation energy. To select the appropriate operand bit-widths that achieve significant reduction of power consumption with minimum image quality degradation, we also propose a bit-width selection algorithm. The proposed variable bit precision DCT algorithm can be efficiently implemented using carry save adder trees. The reconfigurable DCT architecture can achieve power savings ranging from 36% to 75% compared to normal operation at the expense of minor image quality degradation.

An Arbitrary-length and Multiplierless DCT Algorithm and Systolic Implementation

Discrete Cosine transform (DCT) is an important tool in digital signal processing. In this paper, a novel algorithm to perform DCT multiplierlessly is proposed. First, by modular mapping and truncating Taylor series expansion, the DCT is expressed in the form of the product of the constants and discrete moments. Second, by performing appropriate bit operations and shift operations in binary system, the product can be transformed to some additions of integers. The proposed algorithm only involves integer additions and shifts because the discrete moments can be computed only by integer additions. An efficient and regular systolic array is designed to implement the proposed algorithm , and the complexity analysis is also given. Different to other fast Cosine transforms, our algorithm can deal with arbitrary length signals and get high precision. The approach is also applicable to multi-dimensional DCT and DCT inverses.

Novel DCT-Based Real-Valued Discrete Gabor Transform and Its Fast Algorithms

The oversampled Gabor transform is more effective than the critically sampled one in many applications. The biorthogonality relationship between the analysis window and the synthesis window of the Gabor transform represents the completeness condition. However, the traditional discrete cosine transform (DCT)-based real-valued discrete Gabor transform (RGDT) is available only in the critically sampled case and its biorthogonality relationship for the transform has not been unveiled. To bridge these important gaps, this paper proposes a novel DCT-based RDGT, which can be applied in both the critically sampled case and the oversampled case, and their biorthogonality relationships can be derived. The proposed DCT-based RDGT involves only real operations and can utilize fast DCT algorithms for computation, which facilitates computation and implementation by hardware or software as compared to that of the traditional complex-valued discrete Gabor transform. This paper also develops block time-recursive algorithms for the efficient and fast computation of the RDGT and its inverse transform. Unified parallel lattice structures for the implementation of these algorithms are presented. Computational complexity analysis and comparisons have shown that the proposed algorithms provide a more efficient and faster approach for discrete Gabor transforms as compared to those of the existing discrete Gabor transform algorithms. In addition, an application in the noise reduction of the nuclear magnetic resonance free induction decay signals is presented to show the efficiency of the proposed RDGT for time-frequency analysis.

Encrypted Domain DCT Based on Homomorphic Cryptosystems

Signal processing in the encrypted domain (s.p.e.d.) appears an elegant solution in application scenarios, where valuable signals must be protected from a possibly malicious processing device. In this paper, we consider the application of the Discrete Cosine Transform (DCT) to images encrypted by using an appropriate homomorphic cryptosystem. An s.p.e.d. 1-dimensional DCT is obtained by defining a convenient signal model and is extended to the 2-dimensional case by using separable processing of rows and columns. The bounds imposed by the cryptosystem on the size of the DCT and the arithmetic precision are derived, considering both the direct DCT algorithm and its fast version. Particular attention is given to block-based DCT (BDCT), with emphasis on the possibility of lowering the computational burden by parallel application of the s.p.e.d. DCT to different image blocks. The application of the s.p.e.d. 2D-DCT and 2D-BDCT to 8-bit greyscale images is analyzed; whereas a case study demonstrates the feasibility of the s.p.e.d. DCT in a practical scenario.

Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures

We present an algorithmically-aware, high-level partitioning methodology for discrete cosine transforms (DCT) targeted to distributed hardware architectures. The methodology relies on the exploration of alternate DCT formulations as part of the partition optimization process. To the best of our knowledge, no previously proposed DCT algorithm exists that is capable of consistently producing alternate regular formulations for an n-size DCT. Hence, a new Cooley-Tukey-like DCT factorization algorithm was developed to allow exploration of alternate formulations as part of the partitioning optimization process. The use of our factorization mechanism along with a greedy strategy to explore the space of equivalent DCT formulations yielded partitioning solutions with as much as 18% reduction in latency and 83% reduction in run-time as compared to previously proposed regular DCT formulations.

Fast Three-Dimensional Discrete Cosine Transform

A fast three-dimensional discrete cosine transform algorithm (3D FCT) and a fast 3D inverse cosine transform (3D IFCT) algorithm are presented, suitable for analysis of 3D data points. Many existing algorithms for three-dimensional data points make use of either the 1D cosine transform or both the 2D and 1D cosine transforms. Existing algorithms based on the 1D discrete cosine transform (DCT) apply the separable 1D transform to the data points in the x, y, and z directions, respectively, while those based on 2D and 1D transforms apply the 2D cosine transform for the x-y planes and then the 1D cosine transform in the z direction. The proposed 3D DCT algorithms handle the 3D data points directly and have been shown to be computationally efficient. They involve a 3D decomposition process where a data volume is recursively decomposed in each dimension until unit data cubes are obtained. The algorithms are presented in the form of a signal flow graph which captures the various computations involved. A complexity analysis along with empirical results is included, demonstrating the performance of the proposed direct 3D DCT algorithms. As 3D FCT and IFCT are symmetric and relatively fast, they can be used in any application requiring a real-time symmetric codec, such as video conferencing, online multiparty video games, and three-dimensional graphics rendering.

Fast Radix- $q$ and Mixed-Radix Algorithms for Type-IV DCT

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This letter proposes a fast radix-$q$ algorithm to compute type-IV discrete cosine transform (DCT) of the length $q ^{\lambda}$, where $q$ is an odd positive integer. The proposed fast radix- $q$ algorithm has merits in computational complexity, parallelism, and numerical stability over existing algorithms. Furthermore, the fast radix-$q$ algorithm is used to develop the fast mixed-radix type-II/type-IV DCT algorithm for composite lengths. </para>

Roundoff error analysis of fast DCT algorithms in fixed point arithmetic

Discrete cosine transforms (DCT) are essential tools in numerical analysis and digital signal processing. Processors in digital signal processing often use fixed point arithmetic. In this paper, we consider the numerical stability of fast DCT algorithms in fixed point arithmetic. The fast DCT algorithms are based on known factorizations of the corresponding cosine matrices into products of sparse, orthogonal matrices of simple structure. These algorithms are completely recursive, are easy to implement and use only permutations, scaling, butterfly operations, and plane rotations/rotation-reflections. In comparison with other fast DCT algorithms, these algorithms have low arithmetic costs. Using von Neumann–Goldstine’s model of fixed point arithmetic, we present a detailed roundoff error analysis for fast DCT algorithms in fixed point arithmetic. Numerical tests demonstrate the performance of our results.

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

This paper reports an efficient Discrete Cosine Transform (DCT) processing method for images using a massive-parallel memory-embedded SIMD matrix processor. The matrix-processing engine has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. For compatibility with this matrix-processing architecture, the conventional DCT algorithm has been improved in arithmetic order and the vertical/horizontal-space 1 Dimensional (1D)-DCT processing has been further developed. Evaluation results of the matrix-engine-based DCT processing show that the necessary clock cycles per image block can be reduced by 87% in comprison to a conventional DSP architecture. The determined performances in MOPS and MOPS/mm2 are factors 8 and 5.6 better than with a conventional DSP, respectively.