Direct Wafer Bonding Research Articles

3D 적층 IC를 위한 웨이퍼 레벨 본딩 기술

(2013년 2월 21일 접수: 2013년 3월 18일 수정: 2013년 3월 25일 게재확정 )Abstract: 3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. ICcan be stacked through various bonding technologies and they were reviewed in this report, for example, wafer directbonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were requiredfor high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquidinter-diffusion and direct bonding interface technologies are actively being developed.Keywords: 3D IC, wafer level stacking, thermo-compression, bonding

Effects of Wet Activation Process Parameters on Surface Hydrophilicity in Silicon Direct Wafer Bonding

Wet activation is a very important step in silicon direct wafer bonding process and a optimized activation process is desirable to improve the surface hydrophilicity. Therefore the pivotal parameters of activation process were investigated which were volume ratio, holding time and treat temperature. A orthogonal experiment array was designed to reveal the effects of these parameters and the experiment results were analyzed by range analysis method. The analysis results indicted among those three parameters, everyone had intimidate relationship with surface hydrophilicity, which was indexed by contact angle. And higher concentration, longer holding time and higher treating temperature in possible value range were more desirable. Based on these conclusions, optimized activation process was desigened using which void-free bonding was realized.

Mechanisms for Ultra-Low Temperature Plasma Activated Direct Wafer Bonding

not Available.

Direct Wafer Bonding and Its Application to Waveguide Optical Isolators.

This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO3. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI) waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

Reconstruction of a High Angle Tilt (110)/(001) Boundary in Si Using O-lattice Theory

High angle close to 90° tilt Si boundary created by direct wafer bonding (DWB) using SmartCut® technology is studied in this work. Experimental identification of defects and morphologies at the interface is realized using conventional transmission electron microscopy (TEM) and geometric phase analysis (GPA) of high-resolution TEM images. Atom reconstruction of the interface along the direction is carried out within the frame of the O-lattice theory. We demonstrate that to preserve covalent bonding across the interface it should consist of facets intersected by a maximum of six planes with three 90° Shockley dislocations per facet. For a long enough interface the formation of Frank dislocations is predicted with a period equal 6 times that of Shockley dislocations. Long range undulations of the interface are shown to be related directly to a deviation from exact 90° tilt of the layer with respect to the substrate.

Effect of Ultra Violet Process and Annealing on Reliability in Low Temperature Silicon Wafer Direct Bonding

Effect of Ultra Violet Process and Annealing on Reliability in Low Temperature Silicon Wafer Direct Bonding

Fabrication of Capacitive Micromachined Ultrasonic Transducers via Local Oxidation and Direct Wafer Bonding

We present the successful fabrication of capacitive micromachined ultrasonic transducers (CMUTs) with an improved insulation layer structure. The goal is to improve device reliability (electrical breakdown) and device performance (reduced parasitic capacitance). The fabrication is based on consecutive thermal oxidation steps, on local oxidation of silicon (LOCOS), and on direct wafer bonding. No chemical-mechanical polishing step is required during the device fabrication. Aside from the advantages associated with direct wafer bonding for CMUT fabrication (simple fabrication, cell shape flexibility, wide gap height range, good uniformity, well-known material properties of single-crystal materials, and low intrinsic stress), the main vertical dimension (electrode separation) is determined by thermal oxidation only, which provides excellent vertical tolerance control ( <;10 nm) and unprecedented uniformity across the wafer. Thus, we successfully fabricated CMUTs with gap heights as small as 40 nm with a uniformity of ±2 nm over the entire wafer. This paper demonstrates that reliable parallel-plate electrostatic actuators and sensors with gap heights in the tens of nanometer range can be realized via consecutive thermal oxidation steps, LOCOS, and direct wafer bonding without chemical-mechanical polishing steps.

High Quality Thin Body III-V-On-Insulator Channel Layer Transfer on Si Wafer Using Direct Wafer Bonding

Integration of III-V semiconductor compounds into Si wafers has been paid match attention because of requirements of the high electron mobility and low effective mass channel materials instead of Si and requirements for monolithic integration of the electrical and optical integration. However, it has been still challenging due to several differences between III-V semiconductor compounds and Si in material properties: lattice constant, thermal tolerance, and material toughness. Therefore, for fabricating thin body III-V-on-insulator (III-V-OI) on Si wafers with retaining the high crystal quality, we have developed low damage and low temperature direct wafer bonding (DWB) processes using buried oxide protection layers. We have demonstrated high electron channel mobility thin body III-V-OI metal-oxide-semiconductor field-effect transistors (MOSFETs) on Si substrates. The transistor property has exceeded the Si MOSFETs and comparable to the bulk III-V MOSFETs, indicating that we can transfer the high crystal quality III-V-OI channel layers using these DWB processes.

Investigation of Sulfur Passivation Treatments for Direct Wafer Bonding of III-V Materials

Bonding techniques for direct wafer bonding of III-V materials by various sulfur passivation treatments are presented. A dry sulfur passivation method utilizing elemental sulfur vapor activated by ultraviolet light in high vacuum is adapted for use in wafer bonding. Large area bonding is achieved for GaAs/GaAs and InP/InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively without large compressive forces. X-ray photoelectron spectroscopy measurements of the treated GaAs surface show the reduction of oxide and creation of sulfide bonds prior to bonding. The electrical conductivity across a sulfur bonded GaAs/GaAs interface is greatly improved with a short anneal (1-2 minutes) at elevated temperatures (500-600 °C) and HRTEM images reveal the interface is restructuring at lower temperatures than reported for other bonding techniques.

Investigation of Sulfur Passivation Treatments for Direct Wafer Bonding of III-V Materials

not Available.

Dynamics of Contact Wave in Silicon Wafer Direct Bonding

A quantitative description of the dynamics of silicon wafer direct bonding is proposed, and the contact wave for bonding front propagation is modeled as a function of time. The changes in exhaust gas power, accumulated deformation power and wafer surface energy during bond processing have been studied systematically, and the governing differential equation of the contact wave position is deduced from the law of conservation of energy. The relationship of wave front position to the height of gas gap between bonded wafers is derived. Moreover, the functional dependence of contact wave position and bonding wave velocity on time is investigated, and the average wave velocity is obtained. The model describes well the experimental data available from literatures, and provides a basis for silicon wafer direct bonding process optimization.

Fabrication of GaAs on Si Heterostuctures by Helium Implantation and Direct Wafer Bonding

Transfer of GaAs layers onto Si by helium ion implantation at room temperature and direct wafer bonding was investigated. The in uence of the ion energy (100 keV and 500 keV), the ion uence and the subsequent annealing condition on exfoliation and/or blistering was studied by using optical microscopy, Rutherford backscattering and channeling spectrometry (RBS/C), X-ray di raction (XRD) and cross-sectional transmission electron microscopy (XTEM) analysis and the optimum conditions for achieving thin layer exfoliation only after post-implantation annealing were experimentally determined. Our results suggest that the optimum uence for the GaAs ion-cut is in the range of (2 { 5) 1017 He+/cm2. Thin 400 GaAs layers were successfully transferred onto silicon after bonding of helium-implanted GaAs and Si wafers via a silicon-oxide intermediate layer and subsequent low-temperature splitting annealing at less than 220 C. Field emission scanning electron microscopy (FE-SEM) showed that a uniform transfer of the GaAs layer onto Si was obtained with no detectable defects at the GaAs/SiO2/Si bonding interfaces. XTEM observations of the as-split GaAs layers revealed that the relatively undamaged layer close to the intermediate layer could be extended by appropriate choices of the bonding process and/or implanted ion energy.

CMP For Direct Wafer Bonding of Hermetically Sealed Cavity Structures

Direct wafer bonding (DWB) is being increasingly utilized for advanced device and packaging applications, but both surfaces must be extremely smooth to achieve a uniform bond. Chemical mechanical polishing (CMP) is the ideal process for pre-bond surface preparation. This work focused on developing a process sequence for DWB of both patterned and unpatterned substrates as part of a project to develop hermetically sealed cavities. Deep cavities were etched into various substrates and a CMP process was developed to achieve a target surface roughness, Ra, below 1 nm on borofloat 33 glass substrates. During the optimization phase, it was found that DWB of a patterned substrate requires not only a smooth contact surface, but also that edge rounding of the patterned cavities be minimized. Finally, a series of samples were prepared and tested for suitability of the final process sequence. Data for bond toughness (J/m2) and hermeticity (MIL-STD-883) clearly show that the technique can produce sealed cavities.

CMP for Direct Wafer Bonding of Hermetically Sealed Cavity Structures - Invited

not Available.

Development of Si Neural Probe with Microfluidic Channel Fabricated Using Wafer Direct Bonding

This paper reports the development of a novel Si neural probe with a microfluidic channel to deliver drugs into neural tissue. We fabricated this Si neural probe using wafer direct bonding. To confirm the fluidic capability of the fabricated Si probe, we demonstrated the ejection of liquid from the microfluidic channel using a syringe pump. We confirmed that the Si probe had sufficient bonding strength to eject liquid. In addition, we investigated the pressure drops in the microfluidic channel. From the results, we observed a linear relationship between the flow rate and the pressure drop. Since this result agreed well with the calculated values, we confirmed that the microfluidic channel was successfully formed by wafer direct bonding.

Mechanism of Thermal Silicon Oxide Direct Wafer Bonding

Thermal silicon oxide-to-oxide bonding was investigated at the nanometer level using X-ray reflectivity, transmission electron microscopy, and infrared absorption spectroscopy. The measurements reveal the stages of the closure mechanism, which are different from standard silicon bonding. Upon annealing, interface water pockets are formed, the contents of which are further dissolved into the oxide, demonstrating that the buried thermal oxide–silicon interface acts as a barrier against water reaction with silicon.

Comparisons of the Hot Carrier Effect in Quasi-Silicon-on-Insulator and Conventional Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated by Reversed Silicon Wafer Direct Bonding

The hot carrier effect in quasi-silicon-on-insulator (SOI) and conventional SOI power metal–oxide–semiconductor field-effect transistors (MOSFETs) was compared on the basis of experimental results. Device degradation caused by the hot carrier effect in the quasi-SOI power MOSFETs proved to be smaller than in the conventional SOI power MOSFETs because the former can suppress the activation of parasitic bipolar transistors.

Control of Time-Dependent Contamination during Bonding of Semiconductor and Optical Substrates

Microcontamination control is a key parameter for enhancing yield in terms of density of voids within the interface of a bonded wafer. One important cause of void density is time-dependent haze (TDH) or surface-particulate defect density. TDH on silicon surfaces is generated by the interaction of organic volatiles with moisture on the silicon surfaces. Sub-micrometer particle defect density, or haze level, is mainly affected by contamination arising from five factors: people, process, equipment, environment, and processing chemicals and gases. Direct wafer bonding (DWB) is a three-step sequence consisting of ultra-clean surface preparation, contacting, and thermal annealing. Contacting is an operation of ultrafine alignment and face-to-face joining of two substrates. Prior to joining, each contacting substrate is chemically cleaned in order to minimize surface haze and particulate contamination. Both sub-micrometer particle density and surface haze can be greatly reduced by point-of-use (POU) microfiltration and purification of deionized (DI) water as well as application of ultra-dilute concentration of ultra-pure chemicals containing extremely low levels of liquid particle counts. Ultra-pure DI water is filtered with a high-efficiency membrane filter that removes particles down to 0.02 micrometer (μm), thus reducing metal ions to sub-parts-per-billion (ppb) levels. As a result, surface haze and sub-micrometer light-point defects density on a contacting surface are minimized to reduce the density of voided or disbonded regions. A 1-μm particle, for instance, can cause a void as large as 1 centimeter (cm) in diameter during the bonding operation. Data is presented in terms of fractional areas of the voided regions for direct silicon wafer-bonded substrates. In addition to semiconductor wafer substrates, surface contamination is discussed for optical substrates such as fused silica. Minimizing microcontamination and TDH on the surface of optical substrates is important in maximizing ultraviolet (UV) transmission rates at wavelengths between 190 and 250 nanometers (nm). Methods and techniques are recommended for minimizing trace levels of surface contamination to improve UV transmission rates. No data for bonding of optical components is included in this study.

Dislocation Networks Formed by Silicon Wafer Direct Bonding

The paper reviews methods of hydrophobic wafer bonding. Hydrophobic surfaces are obtained by removing the oxide layer from the surfaces of crystalline silicon substrates. Bonding such surfaces causes the formation of a dislocation network in the interface. The structure of the dislocation network depends only on the misalignment (twist and tilt components). The different dislocation structures are discussed. Because wafer bonding offers a method to the reproducible formation of such networks, different applications are possible

Scanning probe studies of the electrical activity at interfaces formed by silicon wafer direct bonding

AbstractIn order to investigate the electrical properties at the surface of dislocation rich silicon, we conducted Electrostatic Force Microscopy on cross‐sections of samples prepared by Wafer Direct Bonding. The applied methods, namely Scanning Kelvin Probe Microscopy and non‐contact Scanning Capacitance Microscopy, yield a distinct contrast at the position of the dislocation area, i.e. the bonding interface, indicating strong electrical activity. For an explanation of the explicit electrostatic potential extracted from the experiment a simple model taking into account only an intrinsic charge distribution at the dislocation area appears to be insufficient. Instead, a more complex approach has to be used considering carrier generation and recombination by additional, dynamic mechanisms. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)