Direct Digital Synthesizer Research Articles

Design and memory optimization of hybrid gate diffusion input numerical controlled oscillator

The numerically controlled oscillator (NCO) is one of the digital oscillator signal generators. It can generate the clocked, synchronous, discrete waveform, and generally sinusoidal. Often NCOs care utilized in the combinations of digital to analog converter (DAC) at the outputs for creating direct digital synthesizer (DDS). The network on chips (NOCs) are utilized in various communication systems that are fully digital or mixed signals such as synthesis of arbitrary wave, precise control for sonar systems or phased array radar, digital down/up converters, all the digital phase locked loops (PLLs) for cellular and personal communication system (PCS) base stations and drivers for acoustic or optical transmissions and multilevel phase shift keying/frequency shift keying (PSK/FSK) modulators or demodulators (modem). The basic architecture of NCO will be enhanced and improved with less hardware for facilitating complete system level support to various sorts of modulation with minimum FPGA resources. In this paper design and memory optimization of hybrid gate diffusion input (GDI) numerically controlled oscillator based on field programmable gate array (FPGA) is implemented. compared with NCO based 8-bit microchip, memory optimization of hybrid GDI numerically controlled oscillator based on FPGA gives effective outcome in terms of delay, metal-oxide-semiconductor field-effect transistors (MOSFET’s) and nodes.

Research and Implementation of a Numerical Control Oscillator with Improved Pipelined CORDIC Algorithm

As the recognized core of electronic systems, frequency synthesizers have been applied in many communication fields. NC oscillator (NCO) is the main component of the frequency synthesizer. It helps to generate high-precision and high-frequency signals, so it has been widely used. NCO implementation methods include table lookup method, polynomial expansion method, coordinate rotation digital computer (CORDIC) algorithm, etc. CORDIC algorithm is one of many commonly used methods in trigonometric function calculation and digital signal processing, and is often used as the core of DDS (direct digital synthesis) to generate signals. Compared with table lookup and polynomial expansion, CORDIC algorithm has higher efficiency in signal generation and hardware utilization. In view of the disadvantages of traditional CORDIC algorithm, which takes up large resources and has relatively slow calculation speed, in order to improve the output efficiency, this paper uses an efficient 12-stage pipelined CORDIC architecture and a very small lookup table (LUT) to implement a sine wave generator. The system is coded and simulated in Quartus and ModelSim. The results show that the proposed structure can increase the operating speed of the system from 217.77 MHz to 291.04 MHz, and improve the output efficiency of the system.

Measurement and Control System for Atomic Force Microscope Based on Quartz Tuning Fork Self-Induction Probe.

In this paper, we introduce a low-cost, expansible, and compatible measurement and control system for atomic force microscopes (AFM) based on a quartz tuning fork (QTF) self-sensing probe and frequency modulation, which is mainly composed of an embedded control system and a probe system. The embedded control system is based on a dual-core OMAPL138 microprocessor (DSP + ARM) equipped with 16 channels of a 16-bit high-precision general analog-to-digital converter (ADC) and a 16-bit high-precision general digital-to-analog converter (DAC), six channels of an analog-to-digital converter with a second-order anti-aliasing filter, four channels of a direct digital frequency synthesizer (DDS), a digital input and output (DIO) interface, and other peripherals. The uniqueness of the system hardware lies in the design of a high-precision and low-noise digital-analog hybrid lock-in amplifier (LIA), which is used to detect and track the frequency and phase of the QTF probe response signal. In terms of the system software, a software difference frequency detection method based on a digital signal processor (DSP) is implemented to detect the frequency change caused by the force gradient between the tip and the sample, and the relative error of frequency measurement is less than 3%. For the probe system, a self-sensing probe controller, including an automatic gain control (AGC) self-excitation circuit, is designed for a homemade balanced QTF self-sensing probe with a high quality factor (Q value) in an atmospheric environment. We measured the quality factor (Q value) of the balanced QTF self-sensing probes with different lengths of tungsten tips and successfully realized AFM topography imaging with a tungsten-tip QTF probe 3 mm in length. The results show that the QTF-based self-sensing probe and the developed AFM measurement and control system can obtain high quality surface topography scanning images in an atmospheric environment.

Design and Implementation of Smart Power Voltage and Frequency Synchroniser in Power Distribution System

Voltage and frequency are usually considered and assessed independently in the design and operation of electrical networks. However, these two are linked. Each and every malfunctioning electrical system has an impact on both voltage and frequency. This paper presents the opportunity for monitoring the distributed electrical energy by means of a system that monitors, controls, and provides a breakpoint based on high or low voltage and frequency tripping mechanism that avoids any damage to the load. The designed system comprised a switch mode power supply (SMPS), a direct digital synthesizer (DDS), and PIC16F876A microcontroller techniques for stable voltage and frequency outputs. Proteus design suite version 8.11 software and Benchcope SDS1102CN were used for modeling and simulation. The hardware prototype was implemented at a telecom cell site for data capturing and analysis. Test results showed that the implementation of the prototype provided stable and constant outputs of 222 V/50 Hz and 112 V/60 Hz which constituted 99% and 99.8% efficiency for voltage and frequency performance respectively. The paper also discusses different technologies that can be adopted by the system to mitigate voltage and frequency effects on customer appliances.

A DDS-based integrated microwave source for fast frequency sweeping in quantum magnetic-resonance systems

Magnetic resonance is a fundamental method to manipulate qubits in spin-based quantum information processing. In such areas, the functionality of fast frequency sweeping is required to determine the resonance of the system. We provide a hardware-synchronized sweeping microwave source with a minimal latency in the sub-μs level based on the direct digital synthesizer technique. The output frequency can be up-converted to match the requirement for particular applications. We demonstrate this module in an optically detected magnetic resonance experiment for a nitrogen-vacancy center, and the spectrum is obtained much faster than conventional schemes with high resolution. Comparing with commercial vector signal generators, our module is highly integrated on a single board with a limited area, especially suitable for engineering of quantum sensors and devices in the future.

A Microcontroller-based Liénard Oscillator

Van der Pol Equation is a special case of Liénard equations. Both oscillators have significant historical importance. There are lots of different circuit topologies for Van der Pol and Liénard oscillators. Such oscillators can be made using vacuum tubes, diodes, etc. Some oscillators are made using microcontrollers, which are cheap and easy-to-use devices. They provide accurate adjustability of the frequency and magnitude of the waveforms. Arduino Nano Klon V3.0 microcontroller is a commonly used microcontroller. In this study, to the best of our knowledge, for the first time in literature, a Liénard Oscillator has been made with the Direct digital synthesis (DDS) method using the Arduino Nano Klon V3.0 microcontroller and two DACs. The experimental results of the oscillator are given. The circuit is able to produce the state variables of the oscillator, the effect of quantization can be seen on the waveforms, and it is shown that it performs well. The two variable outputs of the system let its phase portrait be examined easily. Also, using a microcontroller helps to design the oscillator in mere a few days.

A 1.25 MHz, 108 dB Chopped Sampling-Mixer-Based Impedance Spectroscopy SoC in 0.18-μm CMOS

This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes.

A 2-GHz Two-Tone Direct Digital Frequency Synthesizer

We present a 2-GHz 16-bit direct digital synthesizer (DDS) implemented and verified on a Xilinx Artix-7 FPGA, Nexys-4 DDR development board. The lookup-table based DDS is implemented with the help of multiplexers in a tree structure. The proposed technique can operate at a high clock frequency of 250 MHz and has no truncation error. The proposed DDS is also capable of producing two tones separated by a frequency resolution of 1/1024 times the clock frequency. Further, the tones can be backed off in approximately one dB step from full scale to −96 dB. The back-off is implemented without performing any real multiplication thereby increasing the throughput. 16 such parallel DDS slices are implemented to produce very high-frequency digital sinusoids. The design uses 3095 LUTs, 3465 flip flops, and 18 Block-RAMs for producing two tone output at 2GHz for a given back-off.

A Low-Resolution Direct Digital Synthesis Transmitter Architecture Using Dithering for Multiband 5G NR Mobile Applications

This letter presents a low-resolution multiband transmitter architecture using direct digital synthesis (DDS) with dithering. Modern modulated signals constructed by a low-resolution digital-to-analog converter (DAC) suffer from quantization errors and distortions. The proposed technique reduces the quantization problems with the use of a proper oversampling ratio (OSR) and the dithering technique. This technique has lower cost and lower complexity compared to conventional transmitters while maintaining linearity performance. A 50-MHz 5G NR 256-quadratic-amplitude modulation (QAM) signal is used for concept validation at bands n1, n40, and n50. The proposed work achieved the adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of under −30 dBc and 3.5%, respectively. A single 3-bit 10-GS/s radio frequency (RF) DAC is used where the performance is similar to a conventional transmitter using a pair of 5-bit baseband in-phase and quadrature (IQ) DACs.

A Flexible Near-Field Biosensor for Multisite Arterial Blood Flow Detection

Modern wearable devices show promising results in terms of detecting vital bodily signs from the wrist. However, there remains a considerable need for a device that can conform to the human body's variable geometry to accurately detect those vital signs and to understand health better. Flexible radio frequency (RF) resonators are well poised to address this need by providing conformable bio-interfaces suitable for different anatomical locations. In this work, we develop a compact wearable RF biosensor that detects multisite hemodynamic events due to pulsatile blood flow through noninvasive tissue-electromagnetic (EM) field interaction. The sensor consists of a skin patch spiral resonator and a wearable transceiver. During resonance, the resonator establishes a strong capacitive coupling with layered dielectric tissues due to impedance matching. Therefore, any variation in the dielectric properties within the near-field of the coupled system will result in field perturbation. This perturbation also results in RF carrier modulation, transduced via a demodulator in the transceiver unit. The main elements of the transceiver consist of a direct digital synthesizer for RF carrier generation and a demodulator unit comprised of a resistive bridge coupled with an envelope detector, a filter, and an amplifier. In this work, we build and study the sensor at the radial artery, thorax, carotid artery, and supraorbital locations of a healthy human subject, which hold clinical significance in evaluating cardiovascular health. The carrier frequency is tuned at the resonance of the spiral resonator, which is 34.5 ± 1.5 MHz. The resulting transient waveforms from the demodulator indicate the presence of hemodynamic events, i.e., systolic upstroke, systolic peak, dicrotic notch, and diastolic downstroke. The preliminary results also confirm the sensor's ability to detect multisite blood flow events noninvasively on a single wearable platform.

Online Quartz Crystal Microbalance Analyzing Device of Mass Concentration of Formaldehyde Gas Based On FPGA

As one of the main indoor gas pollutants, formaldehyde gas (HCHO) seriously threatens human health and ranks second among toxic chemicals in China. In order to monitor the concentration of formaldehyde in the environment in real time, an online Quartz Crystal Microbalance (QCM) analyzing device based on FPGA is developed in this paper. This device is composed of QCM sensor module and FPGA signal processor. Firstly, graphene oxide film is prepared on QCM chip to adsorb formaldehyde, which causes the change of resonance frequency. Secondly, to monitor the quality of adsorbed formaldehyde through frequency change, FPGA signal processor is mainly integrated with Direct Digital Synthesis module, Analogue-to-Digital Conversion module, Low-Pass Filter module and Frequency Domain Analysis module. These modules have the characteristics of high speed, low power consumption and parallel processing, which provide the best solution for the online implementation of the analyzing device. Finally, the standard gas experiment shows that the device is feasible and reliable for the analysis of formaldehyde gas mass concentration, with a resolution of about 10 counts per 1% concentration.

Frequency-Modulated Signal Measurement Using Closed-Loop Methodology.

Frequency-modulated (FM) signals are widely used in sensing, measurement, and signal detection due to their strong anti-interference and easy transmission characteristics. Although the high-precision measurement methods for static signals are quite complete, the high-precision measurement methods for dynamic FM signals still need to be studied, and the measurement accuracy in the high-sampling system still has room for improvement. Traditionally, the equal-precision measurement method is widely applied in most scenarios. However, its accuracy is limited by the quantization error of ±1 word and the sampling gate time, making it difficult to improve the frequency measurement accuracy while ensuring a high sampling rate at the same time. In this paper, a high-precision feedback frequency measurement system with the capability to eliminate the quantization error of ±1 word is proposed. The proposed system consists of two stages, the rough measurement stage based on the equal-precision measurement method and the precise measurement stage based on the negative feedback tracking architecture using the phase–frequency detector (PFD) and direct digital synthesizer (DDS). The effectiveness and feasibility of the system are verified by both simulation and experiment. At the sampling rate of 2 kHz, the frequency measurement accuracy is improved by more than 30 dB.

Measurement and control of a superconducting quantum processor with a fully integrated radio-frequency system on a chip.

We describe a digital microwave platform called Presto, designed for measurement and control of multiple quantum bits (qubits) and based on the third-generation radio-frequency system on a chip. Presto uses direct digital synthesis to create signals up to 9GHz on 16 synchronous output ports, while synchronously analyzing responses on 16 input ports. Presto has 16 DC-bias outputs, four inputs and four outputs for digital triggers or markers, and two continuous-wave outputs for synthesizing frequencies up to 15GHz. Scaling to a large number of qubits is enabled through deterministic synchronization of multiple Presto units. A Python application programming interface configures a firmware for synthesis and analysis of pulses, coordinated by an event sequencer. The analysis integrates template matching (matched filtering) and low-latency (184-254ns) feedback to enable a wide range of multi-qubit experiments. We demonstrate Presto's capabilities with experiments on a sample consisting of two superconducting qubits connected via a flux-tunable coupler. We show single-shot readout and active reset of a single qubit; randomized benchmarking of single-qubit gates showing 99.972% fidelity, limited by the coherence time of the qubit; and calibration of a two-qubit iSWAP gate.

An Accurately Steerable, Compact Phased Array System for Narrowbeam Ultrasound Transmission

For over more than a decade, ultrasound phased arrays have been playing a leading role in domains such as noninvasive diagnostic examination, nondestructive testing and sonar, and will continue to be indispensable in a wide range of new applications. Unlike the aforementioned traditional scanning systems, many new applications require a transmit-only configuration and work in the low ultrasound frequency range, consequently posing new challenges in low-cost phased array design. However, two sought-after features are still missing in current low-cost ultrasound phased array systems, namely broadband transmission and wide angular beam steering. In this work, a low-cost ultrasound phased array system is presented that enables the transmission of both narrowband and broadband signals. Accurate beam steering is achieved through the concept of Direct Digital Synthesis (DDS). The design features small, wide bandwidth MEMS transducers enabling grating lobe free beam patterns at high frequency and a broad angular beam steering range. The presented prototype supports 64 speaker elements and allows very fine amplitude and phase control over each transducer stage with respectively 10-bit and 12-bit resolution. The beam steering performance is validated for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${1}\times {10}$ </tex-math></inline-formula> calibrated uniform linear array design. In these measurements, an accuracy in the order of just a few degrees was observed, even at a steering angle of 70° off-axis.

Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer’s performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636[Formula: see text][Formula: see text]m2, the power is achieved as 50.125[Formula: see text][Formula: see text]W and delay is attained to be 1.280[Formula: see text]ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques.

Discovering Chaos-Based Communications by Recurrence Quantification and Quantified Return Map Analyses

Many studies show the possibility of transmitting messages in a protected and covert manner using a noise-like chaotic waveform as a carrier. Among popular chaotic communication system (CCS) types, one may distinguish chaotic shift keying (CSK) and parameter modulation (PM) which are based on the manipulation of the transmitting chaotic oscillators. With the development of direct digital synthesis (DDS), it became possible to modulate chaotic signals by varying the properties of the numerical method used in digital chaos generators. The symmetry coefficient modulation (SCM) is such an approach potentially able to provide higher secrecy. However, the actual security of chaos-based communications is still a questionable and controversial feature. To quantitatively evaluate the CCS security level, a certain numerical metric reflecting the difficulty of breaking a communication channel is needed. Return maps are commonly used to attack chaotic communication systems, but the standard algorithm does not involve any kind of quantification. In this study, we propose a new method for estimating the differences between two return maps based on a two-dimensional (2D) histogram. Then, we investigate the resistance of chaotic shift keying, parameter modulation, and SCM communication schemes against three types of attacks: the proposed quantified return map analysis (QRMA), recurrence quantification analysis (RQA), which had not been previously reported for attacking chaos-based communications, and the classical approach based on spectral analysis. In our experiments we managed to recover the plain binary message from the waveform in the channel when transmitted using all three chaos-based messaging techniques; among them, SCM appeared to be the most secure communication scheme. The proposed QRMA turned out to be the most efficient technique for message recovery: the sensitivity of the QRMA appeared to be 2–5 times higher than that in the case of spectral analysis. The proposed QRMA method can be efficiently used for evaluating the difficulty of hacking chaos-based communication systems. Moreover, it is suitable for the evaluation of any other secure data transmission channel.

The Design of DDS ADPLL using ARM Micro Controller

Abstract: Abstract In this article, a full custom design and implementation of a sine wave All Digital Phase Lock Loop (ADPLL) system based on ARM microcontroller is described. These ADPLL implementations are also referred as Software - Direct Digital Synthesis ADPLL (DDS-ADPLL). In the literature, the work related to software DDS ADPLLs is to achieve a specific transient response or dynamic behavior. However, there are few literature that addresses the issues encountered while implementing the Sine wave ADPLL on hardware. This work identifies the problem one may face while implementing the DDS-ADPLLs on microcontroller and proposes methods / solutions to mitigate those issues. Moreover, in order to minimize jitter it is proposed to use timer interrupts and integer datatype. The design procedure of this work uses only integer datatype forimplementation. Keywords: DDS ADPLL; ADPLLs; All Digital PLL; Phase Locked Loop; LPC2148ADPLL

A portable NMR platform with arbitrary phase control and temperature compensation.

In this paper, we present a custom-designed nuclear magnetic resonance (NMR) platform based on a broadband complementary metal-oxide-semiconductor (CMOS) NMR-on-a-chip transceiver and a synchronous reference signal generator, which features arbitrary phase control of the excitation pulse in combination with phase-coherent detection at a non-zero intermediate frequency (IF). Moreover, the presented direct digital synthesis (DDS)-based frequency generator enables a digital temperature compensation scheme similar to classical fieldlocking without the need for additional hardware. NMR spectroscopy and relaxometry measurements verify the functionality of the proposed frequency reference and temperature compensation scheme as well as the overall state-of-the-art performance of the presented system.

Design of A Multifunctional Micro-Magnetic Testing Instrument

Micro-magnetic testing technology is capable of non-destructively evaluating the mechanical properties and residual stress in ferromagnetic components. In the applications of micro-magnetic testing technology, several types of magnetic signals, such as magnetic Barkhausen noise, incremental permeability, tangential magnetic field and eddy current, etc., are used to characterize the target properties (mechanical properties and residual stress). In this paper, a unique framework for multifunctional micro-magnetic sensor design is proposed. Accordingly, a multifunctional micro-magnetic instrument is developed. Intermittently superimposed magnetic fields of high (several kHz) and low frequencies (several Hz) are used for material magnetization. Combined magnetic sensors are employed to measure a total of five types of signals, including the magnetic Barkhausen noise, incremental permeability, eddy currents, tangential magnetic field and main flux. Especially, twisted-pair wiring was used for winding two identical sensing coils. One of the sensing coils is used for eddy current or incremental permeability detection and the rest one acts as a compensatory coil to suppress the strong mutual induction voltage in detection coil. The entire instrument is composed of a multi-channel signal generator, a power amplifier, signal processing circuits embedded into the multifunctional sensor and a four-channel signal acquisition device. The multi-channel signal generator is constructed based on FPGA and high speed D/A converters. The direct digital synthesizer and state machine are programed in FPGA to enable the excitation of intermittently superimposed signals of high and low frequencies. Carefully experiments were performed to test the performances of the developed instrument. The results obtained from different types of steels proved that the developed instrument can acquire five types of magnetic signals with high SNR. The features of the five types of magnetic signals can used to distinguish the material and its mechanical properties such as surface hardness.

An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer.

A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from −43.1 dBc to roughly −59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around −81 dBm.