Direct Digital Frequency Synthesizer Research Articles

Development of a high-voltage radio frequency power supply for quadrupole mass spectrometers with a wide dynamic measurement range

The core component of a quadrupole mass spectrometer is the quadrupole mass filter, serving a crucial role in ion analysis. It operates by applying two sets of high-voltage, high-frequency signals with equal amplitude and opposing phases through the radio frequency power supply, capitalizing on variations in the electric field and differences in mass-to-charge ratios to separate incoming ions. This study leverages direct digital frequency synthesis technology and multi-stage voltage amplification techniques to design a tailored radio frequency power supply for quadrupole mass spectrometers with a broad mass range. Practical testing demonstrates that this power supply generates radio frequency high-voltage signals with a peak-to-peak voltage ranging from 2.210 V to 4.220 kV at a resonant frequency of 1.240 MHz, facilitating the separation of ions with distinct m/z values. Furthermore, the radio frequency power supply is integrated into a Self-developed quadrupole mass spectrometer, enabling an assessment of the mass range, resolution, stability of the spectrometer. The results of these assessments confirm that the developed power supply accommodates scanning of m/z value ions in the range of 1 to 1067 while maintaining an absolute resolution of less than m/z = 1 units and an instrument stability of 2.00% over four hours.and keywords.

Real-Time Implementation of a Frequency Shifter for Enhancement of Heart Sounds Perception on VLIW DSP Platform

Auscultation of heart sounds is important to perform cardiovascular assessment. External noises may limit heart sound perception. In addition, heart sound bandwidth is concentrated at very low frequencies, where the human ear has poor sensitivity. Therefore, the acoustic perception of the operator can be significantly improved by shifting the heart sound spectrum toward higher frequencies. This study proposes a real-time frequency shifter based on the Hilbert transform. Key system components are the Hilbert transformer implemented as a Finite Impulse Response (FIR) filter, and a Direct Digital Frequency Synthesizer (DDFS), which allows agile modification of the frequency shift. The frequency shifter has been implemented on a VLIW Digital Signal Processor (DSP) by devising a novel piecewise quadratic approximation technique for efficient DDFS implementation. The performance has been compared with other DDFS implementations both considering piecewise linear technique and sine/cosine standard library functions of the DSP. Piecewise techniques allow a more than 50% reduction in execution time compared to the DSP library. Piecewise quadratic technique also allows a more than 50% reduction in total required memory size in comparison to the piecewise linear. The theoretical analysis of the dynamic power dissipation exhibits a more than 20% reduction using piecewise techniques with respect to the DSP library. The real-time operation has been also verified on the DSK6713 rapid prototyping board by Texas Instruments C6713 DSP. Audiologic tests have also been performed to assess the actual improvement of heart sound perception. To this aim, heart sound recordings were corrupted by additive white Gaussian noise, crowded street noise, and helicopter noise, with different signal-to-noise ratios. All recordings were collected from public databases. Statistical analyses of the audiological test results confirm that the proposed approach provides a clear improvement in heartbeat perception in noisy environments.

R&D of an Innovative OFDM Communication Payload for Small-Size AUV

With its superiorities of low cost, high flexibility and deployment convenience, small-size autonomous underwater vehicles (AUVs) have been extensively applied to perform a variety of undersea missions. While underwater acoustic (UWA) communication provides a practical way to establish a wireless link, it still poses a significant challenge due to the strict limitations of a small-size AUV platform in terms of load capacity, energy supply and cost. Orthogonal frequency division multiplexing (OFDM) has drawn extensive attention due to its high data rate capability and relative robustness to multipath, the performance of which is unfortunately sensitive to the widespread Doppler effect. While efficient Doppler compensation is significantly crucial for UWA OFDM mobile communication, most of the conventional approaches are conducted using software resampling, thus rendering a huge burden on memory and calculation capability as well as a considerable processing delay. In this paper, from the perspective of hardware completion an UWA OFDM communication payload based on STM32F407 processor is designed and implemented to facilitate agile Doppler compensation with low computational overhead. In particular, after estimating Doppler by calculating the time compression or extension of the preamble signal, Doppler compensation is performed by directly adjusting the direct digital frequency synthesizer (DDS)-driven sampling rate of the analog-to-digital converter (ADC). As the Doppler is compensated parallel to the ADC acquisition, processing delay and memory requirement can be avoided. Finally, hardware-in-loop (HIP) simulation is performed to demonstrate the effectiveness and superiority of the proposed system. The results show that the designed system has the potential to achieve an effective communication rate of 3.19 kbps with the admissible implementation overhead. Future work will entail the integration and performance evaluation of the proposed UWA OFDM communication payload on a practical small-size AUV platform.

Measurement and Control System for Atomic Force Microscope Based on Quartz Tuning Fork Self-Induction Probe.

In this paper, we introduce a low-cost, expansible, and compatible measurement and control system for atomic force microscopes (AFM) based on a quartz tuning fork (QTF) self-sensing probe and frequency modulation, which is mainly composed of an embedded control system and a probe system. The embedded control system is based on a dual-core OMAPL138 microprocessor (DSP + ARM) equipped with 16 channels of a 16-bit high-precision general analog-to-digital converter (ADC) and a 16-bit high-precision general digital-to-analog converter (DAC), six channels of an analog-to-digital converter with a second-order anti-aliasing filter, four channels of a direct digital frequency synthesizer (DDS), a digital input and output (DIO) interface, and other peripherals. The uniqueness of the system hardware lies in the design of a high-precision and low-noise digital-analog hybrid lock-in amplifier (LIA), which is used to detect and track the frequency and phase of the QTF probe response signal. In terms of the system software, a software difference frequency detection method based on a digital signal processor (DSP) is implemented to detect the frequency change caused by the force gradient between the tip and the sample, and the relative error of frequency measurement is less than 3%. For the probe system, a self-sensing probe controller, including an automatic gain control (AGC) self-excitation circuit, is designed for a homemade balanced QTF self-sensing probe with a high quality factor (Q value) in an atmospheric environment. We measured the quality factor (Q value) of the balanced QTF self-sensing probes with different lengths of tungsten tips and successfully realized AFM topography imaging with a tungsten-tip QTF probe 3 mm in length. The results show that the QTF-based self-sensing probe and the developed AFM measurement and control system can obtain high quality surface topography scanning images in an atmospheric environment.

A 1.25 MHz, 108 dB Chopped Sampling-Mixer-Based Impedance Spectroscopy SoC in 0.18-μm CMOS

This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes.

A 2-GHz Two-Tone Direct Digital Frequency Synthesizer

We present a 2-GHz 16-bit direct digital synthesizer (DDS) implemented and verified on a Xilinx Artix-7 FPGA, Nexys-4 DDR development board. The lookup-table based DDS is implemented with the help of multiplexers in a tree structure. The proposed technique can operate at a high clock frequency of 250 MHz and has no truncation error. The proposed DDS is also capable of producing two tones separated by a frequency resolution of 1/1024 times the clock frequency. Further, the tones can be backed off in approximately one dB step from full scale to −96 dB. The back-off is implemented without performing any real multiplication thereby increasing the throughput. 16 such parallel DDS slices are implemented to produce very high-frequency digital sinusoids. The design uses 3095 LUTs, 3465 flip flops, and 18 Block-RAMs for producing two tone output at 2GHz for a given back-off.

An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer.

A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from −43.1 dBc to roughly −59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around −81 dBm.

Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology

Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.

A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization

This paper presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7 psrms integrated over a 100 MHz bandwidth with 28.25 Hz resolution while consuming less than 3 mW at sampling clock 3.12 GHz. The proposed DDFS is fabricated in a 0.9 V TSMC 7 nm CMOS process and occupies a core area of only 0.014 mm.

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

SQUARE-WAVE FREQUENCY MODULATION IN MICROWAVE SPECTROSCOPY

Subject and Purpose. The frequency modulation (FM)combined with lock-in detection, the technique which is used in microwave spectroscopy for enhancing the sensitivity of measurements, as well as the effects due to standing wavesinthe measuring absorption cell can lead to distortions in the spectral line shapes observed. To ensure the highest possible accuracy derivable from the experimental data, these distortions needto be taken into account. A way of improving theaccuracy is to approximate to the experimental line contour with a theoretical line shape that would account for the observable distortion effects.The relevant literature sources suggest examples of theoretical expressions for the line shape in the case of a sinusoidal frequency modulation. This work has been aimed at derivingsimilar expressions for the case of a square-wave frequency modulation that shall allow increasing the accuracy of measurements. Methods and Methodology.The square-wave-FM signalsare obtained with the aid of a direct digital frequency synthesizer thatcan provide switching between two frequencies known to a high accuracy. This technical solution permits generating FM signals with precisely specified parameters. Results. A closed-form expression has been suggested, based on numerically evaluated line shape derivatives, whichallows taking into considerationthe basic types of distortions encountered in the spectral line records. The cases that have been considered concern a variety of experimental conditions, including sub-Doppler measurements with Lamb-dip observations. Conclusions. The approach that has been proposed allows one to properly take into account the distortions of spectral line shapes resulting from the use of a square-wave-FM signal, as well as those due to standing wave effects in the spectrometer cell. As has been found, application of this approach to experimental spectra with a variety of modulation parameters permits reducing the errors of frequency determination to ±0.001MHz, provided the signal-to-noise ratios are reasonably high.

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering

This brief proposes a high spurious-free dynamic range (SFDR) pulse output direct digital frequency synthesizer (PDDS) with low complexity and low power consumption. Independent and uniformly distributed (IUD) high-pass-shaped dither is added to the phase accumulator output, resulting in a wideband spurious-free and low close-in noise floor. The power efficiency and speed are increased by reducing the sampling frequency of the ${m}$ -sequence generator and the high-pass filter (HPF). The SFDR improves by 29 dB as a result of the HPF, which is confirmed with a field-programmable gate array (FPGA) implementation. The application specified integrated circuit (ASIC) occupies $1168~{\mu \text {m}^{2}}$ on nangate 45-nm CMOS process and consumes 80.2 and $398~{\mu }\text{W}$ from a 1.2-V supply with the dither generator running at ${({1}/{4})f_{\text {clk}}}$ and ${f_{\text {clk}}}$ ( ${f_{\text {clk}}}=2$ GHz), respectively.

Design of sweep frequency signal source in residual stress detection platform based on Zynq

The signal generator based on DDS technology has high frequency and resolution, and is widely used in many fields such as instrument technology, radar, satellite timing, remote control and telemetry, and is one of the important directions of current signal generator research. In order to achieve a cost-effective, high frequency resolution signal source to stimulate the sensors in the residual stress detection system, this paper selects the Zynq-7020 on-chip system to control the 14-bit direct digital frequency synthesis chip AD9954 to obtain a 40Hz~1MHz sinusoidal signal output. Finally, the performance and technical parameters of the system are tested experimentally. The output signal of the signal source is stable, the signal-to-noise ratio is high, and the frequency error is within 0.1%.

Research and design of digital unit for direct digital frequency synthesizer

The direct digital frequency synthesizer (DDS) is a new kind of all digital frequency synthesizer, which has fast frequency switching speed and high frequency resolution. It has been widely used in the field of signal processing. In this article, we analyze the basic principle of DDS and study several methods of phase-amplitude conversion. We use the method of searching ROM table for rough rotation and the optimized CORDIC algorithm based on excess-fours structure for fine rotation to achieve the phase to amplitude conversion. The power consumption and area of the fine rotation element are reduced with the preprocessing of the phrase. The output frequency is increased by using a 4-channel-interpolation structure. After the design is completed, we verify its correctness and evaluate its performance. The results show the phase-amplitude conversion algorithm meets the need of correctness and the DDS can work stably at 1GHz.

Self-Sustainable Long-Range Backscattering Communication Using RF Energy Harvesting

Radio-frequency (RF)-powered backscattering communication (BC) has many advantages, such as low-power consumption, battery-free, small size, low cost, full sealing, manual maintenance-free, and easy mass deployment. However, the weak RF energy harvested and the short BC distance have become the two critical obstacles in the real-world implementation of this potential technology. In this article, we propose a high-sensitivity RF energy harvesting (RFEH) and long-distance BC method, and for the first time, we demonstrate the RF-powered self-sustainable long-distance BC device named RFEH LoRa. In order to improve RFEH sensitivity, an ultralow-power (ULP) consumption voltage monitoring and startup control circuit topology is designed to reduce the power consumption to 245 nanowatt (nW) during the accumulation of RF energy. While in order to increase the BC distance, a direct digital frequency synthesis technology is used to generate a linear frequency modulation square wave sequence conforming to the LoRa specifications based on the ULP microcontroller unit, and the square wave is used to drive an RF switch to achieve long-distance BC of hundreds of meters. Test results show that the instantaneous BC current is as low as 130 microampere ( μA), and the standby current is only 52 nanoampere (nA). RFEH LoRa is implemented with commercial off-the-shelf components. It can self-startup by harvesting RF energy as low as -22.5 dBm, and send its sensing data to the receiver of 381-m away.

Design and Implementation of Ultrafast Broadband Sweep Source based on AD9914

To address a technical difficulty of long scanning cycle of broadband (100 MHz~900 MHz) frequency sweep source, an ultrafast broadband sweep source was designed based on the basic principle of direct digital-frequency synthesis (DDS) theory by using the high-performance DDS chip AD9914. During the design, the DSP28335 chip was used as the control device. The designed source can output 100MHz~900 MHz swept-frequency signals and it can realize sawtooth wave frequency-modulated signals in the shortest cycle (8us) by configuring the digital ramp generator in the chip. Moreover, a microstrip stepped impedance low-pass filter was designed using ADS to eliminate spurious signals in the direct synthesizer and decrease the in-band attenuation, thus making the curve flatter. According to final test and experimental data analysis, the designed sweep source has a large output broadband, short sweeping cycle and strong inhibition of spurious signals. It possesses great application values.

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

DIRECT DIGITAL SYNTHESIZER IN A NEW MATHEMATICAL BASIS

The principles of the construction and operation of a digital synthesizer for direct frequency synthesis with acceleration of computational operations by using a residual class system (RNS) are considered. The specifics of the implementation of the operation of direct and inverse transformations from the positional number system to the number system of the residual classes are described. A mathematical model of a synthesizer with a phase accumulator in the system of residual classes is considered. The ways of designing a digital synthesizer of direct synthesis with a phase accumulator in the RNS system and a sinusoidal DAC are considered. In traditional schemes, the conversion of residuals to the value of an analog signal occurs in several stages, where conversion to a binary system is one of the stages. This procedure degrades the speed of the RNS system, adding additional constraints and increasing the waiting time for the conversion result. Methods of converting from RNS to binary number system for basic operations are considered. A DDS design with a phase accumulator in the residual class system and a converter to an analog signal form without using a slow ROM is proposed. The problems of efficient use of the synthesizer crystal area and reduction of delays in the formation of the output signal are considered. A study of one of the main functional blocks of a direct digital frequency synthesizer, a digital-to-analog converter, has been carried out. The architecture of a direct digital frequency synthesizer with a DAC direct conversion from a non-positional number system to an analog signal is proposed. The main sources of noise generation in digital computational synthesizers of the proposed type are investigated. A mathematical model is proposed for calculating the power spectral density of phase noise, which will allow analyzing the noise characteristics in synthesizers built on the indicated principles.

Development of on-line nondestructive testing device for welding cracks based on piezoelectric ceramic excitation

Perform real-time non-destructive testing of weld damage in various welded structures of steel to determine the degree of weld damage in order to make timely safety warnings to protect human life and property safety. In this paper, piezoelectric ceramics are arranged on both sides of the weld to find the best frequency of the excitation system. The sine signal of this frequency excites the piezoelectric ceramics on one side, and receives and analyzes the response signals of the piezoelectric ceramics on the other side. This paper uses direct digital frequency synthesis technology (DDS), power management circuit, differential amplifier circuit, band-pass filter circuit, phase detection circuit, amplitude detection circuit, etc. to design a system that can perform real-time nondestructive testing. The whole system can measure the changes of these signals in real time, and send the signals to the upper computer remotely. Analysis of these signals can initially determine the size and location of weld damage. The research results show that when the weld in the steel is damaged, the amplitude of the sinusoidal signal propagating through the weld will be attenuated, and the phase difference between the transmitted signal and the received signal will increase. This change is positively correlated with the degree of damage.

Controlling the light wavefront through a scattering medium based on direct digital frequency synthesis technology* *Project supported by the National Key Research and Development Program of China (Grant Nos. 2016YFB0401902 and 2016YFB0402001) and Key-Area Research and Development Program of GuangDong Province, China (Grant No. 2019B010926001).

Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix (TM) of a scattering medium. We report a simple but powerful method, direct digital frequency synthesis (DDS) technology to modulate the phase front of the laser and measure the TM. By judiciously modulating the phase front of a He–Ne laser beam, we experimentally generate a high quality focus at any targeted location through a 2 mm thick 120 grit ground glass diffuser, which is commercially used in laser display and laser holographic display for improving brightness uniformity and reducing speckle. The signal to noise ratio (SNR) of the clear round focus is ∼ 50 and the size is about 44 μm. Our study will open up new avenues for enhancing light energy delivery to the optical engine in laser TV to lower the power consumption, phase compensation to reduce the speckle noise, and controlling the lasing threshold in random lasers.