Direct-coupled Transistor Logic Research Articles

Integrated Circuits Based on Bilayer MoS2 Transistors

Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene’s advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS2 show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS2 to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between 2 to 12 transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS2. Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions.

The total switch time of silicon bipolar transistors with base doping gradients or with germanium gradients in the base

In this paper the total switch time for a transistor in a Direct Coupled Transistor Logic (DCTL) circuit is simulated by using Laplace transformations of the Ebers-Moll equations. The influence of doping gradients and germanium gradients in the base is investigated and their relative importance and their limitations are established. In a well designed bipolar transistor only a minor enhancement of the total switch time is obtained with the use of a doping gradient in the base. However, for bipolar transistors with base thickness over 500 Å, an improperly selected doping profile could be devastating for the total switch time. For a bipolar transistor the improvement of the total switch time due to a linear germanium gradient in the base could be up to about 30% compared with an ordinary silicon bipolar transistor. Still, a too high germanium gradient forces the normal transistor current gain (α N) to grow and the total switch time is thereby increased. Further enhancement could be achieved by the use of a second degree polynomial germanium profile in the base. Also in this case, care must be taken not to enlarge the germanium gradient too much as the total switch time then starts to increase. In all cases the betterment of the base transit time that is introduced by the electric field will not be directly used to reduce the base transit time. Instead the improvement is mostly used to lower the emitter transition charging time. However, the most important parameter to control is the normal transistor current gain (α N) that has to be kept within a narrow range to keep the total switch time low.

New physical timing models of bipolar nonsaturation logic using current-domain analysis technique

A new large-signal equivalent circuit with input and output current signals for a nonsaturated bipolar junction transistor has been developed. Based upon this equivalent circuit, physical timing models of direct-coupled transistor logic (DCTL) and nonthreshold logic (NTL) have been derived through a general modeling methodology. It is shown from extensive comparisons with SPICE simulation results that the models have a maximum error of 25% in single-stage delay calculation and 10% in multi-stage delay calculation. Experimental results on NTL ring oscillators also partly substantiate the developed current-domain large-signal equivalent circuit and physical timing models. Good accuracy, wide applicable ranges of device/circuit parameters and input waveforms, and less CPU time and memory consumption than full transient simulations make the physical timing models feasible in optimization and CAD of high-speed bipolar ICs.

Ring oscillator circuit simulation with physical model for GaAs/GaAlAs heterojunction bipolar transistors

Switching performance is simulated for GaAs/GaAlAs heterojunction bipolar transistors (HBT's) by combining a realistic physical device model that involves numerical solutions for carrier transport equations and Poisson's equation with our own circuit simulator that enables direct access to the device model embedded in arbitrary circuits. Based on simulated results for five-stage ring oscillators, discussion is given as to how the switching performance depends on the circuit configuration such as current mode logic (CML) without and with emitter follower, and direct-coupled transistor logic (DCTL), inclusion or exclusion of external base areas, and choice for single-or double-heterojunction transistors.

Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> P and <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.

Static and dynamic performance of micropower transistor logic circuits

Digital transistor circuits operating in the range (viz., 1 to 1000 µw per gate) are needed in the portable electronic equipments of a modern field army. The most basic micropower transistor requirements are, 1) junction reverse currents which are small compared with minimum operating currents, 2) useable device current gains at minimum operating currents, and 3) minimum junction capacitances in order to enhance switching speed. The micropower performance capabilities of modified direct coupled transistor logic (DCTL), diode transistor logic (DTL) and transistor transistor logic (TTL) circuits are sufficient to satisfy the present and projected requirements of many portable equipment applications. The normal operating temperature range, logic capability, and tolerance immunity of the circuits need not be compromised. Somewhat reduced stability margins may be necessary but are permissible due to lower operating power levels. Markedly reduced operating speeds are unavoidable but not at all detrimental since audio clock frequencies suffice for many portable equipments. In order to maintain adequate over-all performance, a minimum saturated transistor collector current I CS is required in a micropower logic gate. This minimum is most sensitive to the maximum operating temperature of the circuit. The feasibility of implementing a particular micropower circuit design by means of hybrid thin-film techniques or integrated silicon techniques depends principally on the large total circuit resistance values encountered in micropower designs.

Computers in the front lines: micromodules make it possible : A. S. Rettig, Electronics, p. 77 (Jan. 4, 1963)

In this paper the total switch time for a transistor in a Direct Coupled Transistor Logic (DCTL) circuit is simulated by using Laplace transformations of the Ebers-Moll equations. The influence of doping gradients and germanium gradients in the base is investigated and their relative importance and their limitations are established. In a well designed bipolar transistor only a minor enhancement of the total switch time is obtained with the use of a doping gradient in the base. However, for bipolar transistors with base thickness over 500 Å, an improperly selected doping profile could be devastating for the total switch time. For a bipolar transistor the improvement of the total switch time due to a linear germanium gradient in the base could be up to about 30% compared with an ordinary silicon bipolar transistor. Still, a too high germanium gradient forces the normal transistor current gain (αN) to grow and the total switch time is thereby increased. Further enhancement could be achieved by the use of a second degree polynomial germanium profile in the base. Also in this case, care must be taken not to enlarge the germanium gradient too much as the total switch time then starts to increase. In all cases the betterment of the base transit time that is introduced by the electric field will not be directly used to reduce the base transit time. Instead the improvement is mostly used to lower the emitter transition charging time. However, the most important parameter to control is the normal transistor current gain (αN) that has to be kept within a narrow range to keep the total switch time low.

Semiconductor surface phenomena, their causes and effects : E. Bartels, Internat. Eltekon. Rundschau17, Nr.7, S. pp. 345–348 (1963)

In this paper the total switch time for a transistor in a Direct Coupled Transistor Logic (DCTL) circuit is simulated by using Laplace transformations of the Ebers-Moll equations. The influence of doping gradients and germanium gradients in the base is investigated and their relative importance and their limitations are established. In a well designed bipolar transistor only a minor enhancement of the total switch time is obtained with the use of a doping gradient in the base. However, for bipolar transistors with base thickness over 500 Å, an improperly selected doping profile could be devastating for the total switch time. For a bipolar transistor the improvement of the total switch time due to a linear germanium gradient in the base could be up to about 30% compared with an ordinary silicon bipolar transistor. Still, a too high germanium gradient forces the normal transistor current gain (αN) to grow and the total switch time is thereby increased. Further enhancement could be achieved by the use of a second degree polynomial germanium profile in the base. Also in this case, care must be taken not to enlarge the germanium gradient too much as the total switch time then starts to increase. In all cases the betterment of the base transit time that is introduced by the electric field will not be directly used to reduce the base transit time. Instead the improvement is mostly used to lower the emitter transition charging time. However, the most important parameter to control is the normal transistor current gain (αN) that has to be kept within a narrow range to keep the total switch time low.

Reliability in direct coupled transistor logic : A. B. Starks-Field and A. M. King, Marconi Rev.25, 42–46 (1962)

Reliability in direct coupled transistor logic : A. B. Starks-Field and A. M. King, Marconi Rev.25, 42–46 (1962)

Transient analysis of junction transistors

The transient behavior of the surface barrier and diffused junction transistors may be represented by an equivalent network consisting of two diodes and a nonlinear base resistance. Expressions for the nonlinear resistance, the base-emitter voltage time response, and the collector current time response are derived and tested experimentally. The equivalent circuit allows us to predict hole storage time for direct-coupled transistor logic (DCTL) circuits.

Transistor characteristics for direct-coupled transistor logic circuits

The basic requirement for stability of a direct-coupled transistor logic (dctl) circuit is that a voltage margin exist between the maximum collect-emitter voltage of an ''on'' unit in the system environment and the minimum base-emitter voltage required for a transistor to be sufficiently ''off.'' This margin has been expressed in terms of the fundamental device parameters: commonbase forward and inverse current αN and αI; ohmic body resistances of the emitter, collector, and base regions, γ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> ' and γ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ' γ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bIII</sub> ; collector saturation current, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">co</sub> ; and the ratio of the value of α in the vicinity of the ''off'' state to its value in the vicinity of the ''on'' state. In addition, the connection of bases in parallel results in a dependence of stability on the magnitude of α <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</sub> and of γ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bIII</sub> and on the variations of αN, αI, γbIII and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CO</sub> among units connected in this manner. Circuit stability requirements have been expressed in terms of these parameters and the effect of their variations is considered. Methods for the specification of acceptance requirements for dctl transistors and the relation of these specifications to logic design rules are discussed.

Direct-Coupled Transistor Logic Circuitry

Direct-coupled transistor logic circuitry lends itself to systematic design methods and performs remarkably well. Logical design rules are given for use with transistors which meet specifications treated in a companion paper. The implications of the use of silicon transistors are discussed.