Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

Abstract

As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> P and <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .