Direct-coupled Field-effect Transistor Logic Research Articles

Threshold voltage modulation on a CTL-based monolithically integrated E/D-mode GaN inverters platform with improved voltage transfer performance

This work demonstrates a high-performance monolithically integrated GaN inverters platform, which incorporates enhancement-mode (E-mode) and depletion-mode (D-mode) GaN high-electron-mobility transistors (HEMTs) simultaneously using an Al:HfOx-based charge trapping layer. The developed E-mode HEMT exhibits a positive threshold voltage of 2.6 V, a high ON–OFF current ratio of 1.9 × 108, a current density of 376 mA/mm, and an ON-resistance of 15.31 Ω·mm. Moreover, the direct-coupled field-effect-transistor logic (DCFL) GaN inverter was characterized with and without D-mode device threshold voltage (VTH) modulation, demonstrating improved output swing and switching threshold shift by proposed VTH modulation. The optimized DCFL GaN inverter manifests a switching threshold of 2.34 V, a logic voltage output swing of 4.98 V, and substantial logic-low and logic-high noise margins of 2.16 and 2.49 V, respectively, at a supply voltage of 5 V. These results present a promising approach toward realizing monolithically integrated GaN logic circuits for power IC applications.

GaN monolithic digital units on P-GaN platform

Gallium nitride (GaN)-based digital integrated circuits (ICs) are constructed on the commercially available GaN-on-Si wafer designed for pGaN gate HEMT. The functions of inverter, NAND, AND, NOR, and OR logic circuits are successfully realized based on direct-coupled field-effect transistor logic (DCFL) structure. Under a drive voltage of 5V and a load ratio of 20, the low output (VOL) can reach as low as 0.1V. Additionally, a functional-oriented driver, a SR flipflop, and a NOR gate D flipflop are constructed. All the transient tests at a frequency of 100 kHz and temperatures up to 200 °C exhibit satisfying performance characteristics.

Low-Voltage InGaZnO Thin-Film Transistors Gated by SiO<sub>2</sub> Proton Conducting Films

Low-voltage (1.5 V) InGaZnO (IGZO) thin-film transistors (TFTs) gated by the SiO2 proton conducting films were self-assembled by a gradient shadow mask in sputtered self-assembled IGZO channel process. The IGZO TFTs have a high-performance with a large current on/off ratio of ≥1.2×106, a low subthreshold swing of ≤120 mV/decade and a high field-effect mobility of 2.2 ~ 6.9 cm2/V·s. Threshold voltage is tuned by various thicknesses of IGZO channel. Both depletion mode and enhancement mode on the same chip is obtained, which will implement a direct-coupled field-effect transistor logic circuit. Our results demonstrate that the IGZO TFTs are promising logic circuit candidates for portable low-voltage oxide-based devices.

Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications

In this paper, we report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures, a low-resistance <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$n^{+}$</tex></formula> -GaN/2DEG ohmic contact regrown by MBE, a manufacturable 20-nm symmetric and asymmetric self-aligned-gate process, and a lateral metal/2DEG Schottky contact. As a result of proportional scaling of intrinsic and parasitic delays, an ultrahigh <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}$</tex></formula> exceeding 450 GHz (with a simultaneous <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{\rm max}$</tex></formula> of 440 GHz) and a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{\rm max}$</tex></formula> close to 600 GHz (with a simultaneous <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}$</tex></formula> of 310 GHz) are obtained in deeply scaled GaN HEMTs while maintaining superior Johnson figure of merit. Because of their extremely low on-resistance and high gain at low drain voltages, the devices exhibited excellent noise performance at low power. 501-stage direct-coupled field-effect transistor logic ring oscillator circuits are successfully fabricated with high yield and high uniformity, demonstrating the feasibility of GaN-based E/D-mode integrated circuits with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${&gt;}{1000}$</tex> </formula> transistors. Furthermore, self-aligned GaN Schottky diodes with a lateral metal/2DEG Schottky contact and a 2DEG/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n^{+}$</tex></formula> -GaN ohmic contact exhibited <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$RC$</tex></formula> -limited cutoff frequencies of up to 2.0 THz.

Monolithic integrated enhancement/depletion-mode AlGaN/GaN high electron mobility transistors with cap layer engineering

Monolithic integrated enhancement/depletion (E/D)-mode AlGaN/GaN high electron mobility transistors (HEMTs) are fabricated on an AlGaN/GaN heterostructure with an engineered triple-cap-layer. The energy band of the cap layer is greatly tailored by the polarizations within it, which improves the controllability of D-to-E mode conversion with gate recess. The uniformity of the threshold voltage (Vth) across a 3″ wafer is assessed and the standard deviations of Vth are 0.1 V and 0.14 V for E-mode and D-mode devices, respectively. Direct-coupled field-effect transistor logic E/D HEMT inverter and 17-stage ring oscillator are demonstrated, and the latter shows a oscillation frequency of 201 MHz at a supply voltage of 1 V, corresponding to a propagation delay of 146 ps/stage and a power-delay product of 1.96 pJ/stage.

InGaP/InGaAs doped-channel direct-coupled field-effect transistors logic with low supply voltage

InGaP/InGaAs doped-channel direct-coupled field-effect transistor logic (DCFL) with relatively low supple voltage is demonstrated by two-dimensional analysis. In the integrated enhancement/depletion-mode transistors, subband and two-dimensional electron gas (2DEG) are formed in the InGaAs strain channels, which substantially increase the channel concentration and decrease the drain-to-source saturation voltage. The integrated devices show high turn-on voltage, high transconductance, broad gate voltage swing, and excellent high frequency performance, simultaneously. Furthermore, the integrated devices exhibit large noise margins for DCFL application with low supply voltage of 1.5 V attributed from the relatively small saturation voltages of the studied integrated devices.

Self-Aligned Enhancement-Mode and Parasite Depletion-Mode Heterojunction Doped-Channel FET for Low Power Supply DCFL Application

We demonstrate that a heterojunction doped-channel field-effect transistor (HDCFET) structure, using an additional cap layer, simultaneously obtains both p-n junction and Schottky junction to fabricate the enhancement mode and depletion mode of HDCFET (EHDCFET and DHDCFET) on the same chip, thus implementing a direct-coupled field effect transistor logic (DCFL) circuit. In addition, an additional cap layer can perform controllable undercut profile with wet etching to proceed with self-aligned technology resulting in a T-shaped gate structure. The microwave characteristics have also been investigated. The cutoff frequency of the E/D inverter (EDI) is nearly the same with the self-aligned EHDCFET for varied gate-source voltage. When , the cutoff frequency for three self-aligned EHDCFET, parasitic DHDCFET, and EDI are , , and , respectively. The self-aligned EHDCFET dominates the EDI electrical performances. Furthermore, the better inverter performances, the logic-low noise margin and logic-high noise margin, are found to be and , respectively.

Monolithically Integrated Enhancement/Depletion-Mode AlGaN/GaN HEMT Inverters and Ring Oscillators Using$hboxCF_4$Plasma Treatment

Fabrication and characterization of AlGaN/GaN HEMT inverters and ring oscillators utilizing integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN HEMTs are presented. The core technique is a CF4 plasma treatment that can effectively convert a D-mode AlGaN/GaN heterostructure to an E-mode heterostructure. A significant advantage of the plasma-treated E-mode HEMTs is that the gate current is reduced in both reverse- and forward-bias regions due to the effectively enhanced barrier height induced by the negatively charged fluorine ions in the AlGaN barrier. As a result, the input voltage swing is expanded by about 1 V for the E-mode HEMT, enabling convenient input/output logic level matching for multistage logic circuits such as ring oscillators. The fabricated 17-stage direct-coupled field-effect transistor logic ring oscillator using the 1-mum-gate technology can operate properly at a larger supply voltage of 3.5 V, and a minimum propagation delay of 130 ps/stage is achieved

Fast Feedthrough Logic: A High Performance Logic Family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.

Depletion-mode and enhancement-mode InGaP/GaAs δ-HEMTs for low supply-voltage applications

We demonstrate that a new high electron-mobility transistor (HEMT) structure, using an additional n-GaAs cap layer, simultaneously fabricates both the enhancement-mode and depletion-mode of δ-HEMTs on the same chip, thus implementing a direct-coupled field-effect transistor logic circuit. For δ-HEMTs which have a gate dimension of 1 × 100 μm2, the threshold voltage VT for the depletion-mode δ-HEMT is about −1.4 V, while the threshold voltage VT and the maximum applied gate-to-source voltage for the enhancement-mode δ-HEMT are about +0.5 V and +1.6 V, respectively. When VDS = 1.5 V, the output current ID and the gm transconductance are 200 (180) mA mm−1 and 160 (180) mS mm−1, respectively, for the depletion-mode (enhancement-mode) δ-HEMT. The ac characteristics have also been investigated. Furthermore, it is found that better inverter performances can be obtained by using a narrower gate width of the depletion-mode load with a higher supply voltage.

PCFL3: a low-power, high-speed, single-ended logic family

This paper presents a new low-power, high-speed, single-ended logic family called PCFL3. Its operation is based on a bootstrapping technique, used in NMOS. It is fully compatible with direct coupled field-effect transistor logic (DCFL) and two-phase dynamic FET logic (TDFL). PCFL3 is implemented with a standard enhancement/depletion-mode MESFET process and provides all the standard logic functions (NOT, NOR, NAND). Using enhancement-mode FETs only, PCFL3 benefits from good process variation immunity and good noise margins. Measurement results on a ring oscillator are reported. The current consumption of an inverter is reduced by about 53% compared to the DCFL, and the speed is increased by about 50%.

GaAs on silicon grown by molecular beam epitaxy: Progress and applications for selectively doped heterostructure transistors

Recent progress of GaAs-on-Si technology is reviewed and the importance of initial nucleation is emphasized. Growth initiation with a gallium prelayer at a suitable low temperature combined with migration enhanced epitaxy and in-situ thermal annealing may be able to give substantially improved material quality. During the initial growth, use of the minimum necessary As 4:Ga flux ration is found to be critical. Patterned growth or post-growth patterning releases tensile stress only if the growth edges are free. GaAs-on-Si was almost completely relaxed from stress by post-growth patterning to 5 μm × 5 μm size patterns. Steps on the surface owing to substrate misorientation do not affect the two-dimensional electron gas (2DEG) transport properties in AlGaAs/GaAs selectively doped heterojunction transistor (SDHT) structures. For a sheet density of 10 12 cm −2, a 2DEG mobility greater than 50 000 cm 2 V −1 s −1 at 77 K was obtained on silicon substrates, which was found to be adequate for the fabrication of the state-of-the-art devices. For 1 μm-gate-length SDHTs, maximum transconductances of 220 and 365 mS mm −1 were measured at 300 K and 77 K, respectively. A minimum propagation delay time of 28 ps stage −1 was measured at 300 K for direct coupled field effect transistor logic (DCFL) ring oscillators with a power dissipation of 1.1 mW stage −1. The propagation delay time reduced to 17.6 ps stage −1 at 77 K. These results are comparable to the SDHT technology on GaAs substrates.

Folded gate—A novel logic gate structure

We propose a new logic gate structure which consists of two semiconducting layers separated by an insulator. The input electrode is a rectifying contact to the top conducting layer which acts as a channel of a switching field-effect transistor. The bottom conductive layer serves as a load. The conducting layers are connected and capacitively coupled. The top layer acts as a gate for the load element whereas the bottom layer acts as a second gate for the top conductive channel. This folded gate is a majority-carrier device which may be implemented using different technologies and materials. It allows a CMOS-like operation with a very low power consumption in the stable states, speed comparable or higher then the speed of conventional direct-coupled field-effect transistor logic (DCFL), and a larger voltage swing.

Logic Upset Level of GaAs SRAMs for Pulsed Ionizing Radiation

The first pulsed ionizing radiation logic upset measurements on GaAs 256-bit static RAMs are reported and analyzed. The circuit design utilized GaAs enhancement junction field-effect transistors (E-JFETs) with resistive loads and direct-coupled field-effect transistor logic (DCFL). The test results demonstrated upset levels for the most sensitive cells in the range of 6 × 109 to 1 × 1010 rad(GaAs)/s. All evaluated memories contained a core of hard memory cells which retained their logic state up to a dose rate of 3 × 1011 rad(GaAs)/s. A tentative model for memory state upset is presented, which includes the semi-insulating substrate currents generated by ionizing radiation and predicts the observed behavior of the static RAMs tested.

Ionizing Radiation Response of GaAs JFETs and DCFL Circuits

Transient responses and logic upset threshold dose rates of planar, all-ion implanted GaAs E-JFETs and DCFL (= direct-coupled field-effect transistor logic) integrated circuits to ionizing radiation pulses of 20 ns duration from a LINAC are reported. It is experimentally verified that the logic upset dose rate of enhancement mode GaAs JFET integrated circuits is inversely proportional to the square of their channel length. For L = 1 ?m a theoretical value of ?UPSET = 1.175 × 1011 rad (GaAs)/s is predicted and medium scale integrated circuits have confirmed this value with experimental results in the range of 5 × 1010 to 1 × 1011 rad (GaAs)/s. A theoretical relation for logic upset dose rate and a correlation of experimental results with theory is presented. Long term conductance transients are not inherent to E-JFET inverters with resistive and depletion mode JFET load, but are present in source-follower circuits. A model for this circuit behavior will be presented.