Diode Clamped Multilevel Inverter Research Articles

Five-Level Diode Clamped Multilevel Inverter (DCMLI) Based Electric Spring for Smart Grid Applications

This paper presents the multilevel inverter (MLI) based Electric spring (ES) for smart grid applications. Due to the superior performance of Diode-clamped MLI (DCMLI) over other MLI topologies, in this paper ES is realized using 5-level DCMLI. Further the performance of two-level and five-level DCMLI based ES is investigated in terms of Total Harmonic Distortion (THD). It is ascertained that five- level DCMLI achieves voltage regulation with lesser THD in compensated voltage. Moreover, the use of DCMLI based ES as a distributed source is also elaborated. To extract the digitally simulated results and to validate system performance of MLI based ES, detailed simulation studies are carried out using MATLAB environment.

Carrier Shifting Algorithms for the Mitigation of Circulating Current in Diode Clamped MLI fed Induction Motor Drive

Reduction of circulating current is one of the major considerations in inverter fed electrical drives. Diode clamped MLI enables higher output current per phase, thereby rating of the drive gets increased effectively. Various methods of triggering in the inverter legs creates better voltage profile and leads to the enabling of circulating current in the drive system. The induced circulating current flows through the apparatus neutral (N) and supply ground (G) is caused by the existence of parasitic capacitance. This circulating current may cause potential danger especially when parasitic capacitance poses large. In the past, different modulation techniques and conversion topologies have been introduced to minimize the flow of circulating current. However, these techniques lead to complexity, high cost, low voltage profile and efficiency due to lower modulation parameters. This paper proposes PS, POD, PD carrier shifting PWM algorithms for diode clamped MLI to tumbling the circulating current within the each phase of inverter legs. The performances of proposed algorithm, in terms of circulating current, THD, losses and efficiencies are analyzed theoreticallyand are validated via simulation and experimental results.

Artificial neural controller for torque ripple control and maximum power extraction for wind system driven by switched reluctance generator

Abstract Torque ripples and maximum power tracking form the most important problems facing Wind Energy Conversion System (WECS). This paper presents modified toque ripple minimization algorithm of four phases 8/6 poles Switched Reluctance Generator (SRG) using Artificial Neural Network (ANN) control. This control algorithm is based on optimum profiling of the generator phase currents during overlapping periods. The paper, also, introduces new Maximum Power Point Tracking (MPPT) for SRG by modifying the classical Hill Climb Searching (HCL) technique using ANN which is designed to emulate the PI controller for closed loop operation under different wind speeds. Moreover multi level diode clamped inverter is used for connecting SRG to the grid in order to reduce Total Harmonic Distortion (THD) to about 1.45% and reduce filter size. The simulation results show good agreement and support the feasibility of the proposed torque ripple minimization and MPPT techniques.

Electric Vehicle by using Modified Topology of Multilevel Inverter

This paper focused with extends the knowledge in studies and analysis of a new family of diode clamp multilevel inverter for electric vehicle application. The modified new diode clamp multilevel inverter concepts is related to reducing the components utilization, which has (n-1) switching devices, (n-3) clamping diodes, (n-1)/2 DC-link sources for achieving the same voltage level of traditional topologies. The proposed system is enhanced the voltage rating and reduce the total harmonics distortion in inverter output voltage. The switching scheme of Alternatively on Opposition Disposition pulse width modulation strategies is implemented to control multilevel inverter. The proposed system reduces the components utilization which has utilizes 45% of components for achieving the same level of voltage. The modified new diode clamp multilevel inverter is coupled with induction motor and its performance is validated with three phase induction motor for variable frequency drive. The inverter topologies performance has been investigated by prototype model.

Harmonic Analysis of PSO Tuned PI Controller Gains for Multilevel Inverter Base P and O MPPT Photovoltaic System

Objectives: The problem of instability in utilization of energy from PV system and harmonics injection due that is concerned here. The Analyzing of PV system and implementing with suitable techniques to attain permissible THD value is main objective of the work. Methods/Statistical Analysis: In this work for tracking maximum power perturb & observer method is employed. This PV system is integrated using Diode Clamped Multilevel Inverter (DCMLI), for this DCMLI APOD modulation technique is developed. PSA and PSO optimization methods are adopted for PI controller tuning which acts as voltage controller for DCMLI. As PSA is basic and local best optimization technique and PSO for its global best characteristics these methods are opted. Findings: The proposed closed loop system gives better control over open loop system. Tuning of the PI controller plays a crucial role in this closed loop system. In the applied heuristics tuning methods Particle Swarm Optimization (PSO) gives best THD control than Pattern Search Algorithm (PSA). The proposed techniques using PSO optimization is well suitable for PV system as the THD obtained by this is within standard acceptable limits. Actual existing systems like PV system with optimizations employed for MPPT’s or PV system with different multilevel topologies involves more complexity and less output quality than the proposed system. An integrated system is developed i.e. PV with suitable MPPT and multilevel inverter with advanced multilevel modulation tuned with heuristic optimization methods are proposed together for a standalone and also for grid application. Here the proposed system in the area of PV using optimization technique employed for multilevel inverter along with the multilevel modulation technique employed for the DCMLI plays an important role. Application/Improvements: The proposed system is developed based on voltage controller of multilevel inverter it can also be developed along with current controller system. The main objective of this work is to harmonic analysis a PV system with a multilevel inverter in standalone and grid connected mode using PSO and PSA optimization techniques. Keywords: Diode Clamped Multilevel Inverter, Harmonic Analysis, MPPT Technique, Optimization Techniques, PV Array, Tuning of PI Controller

Simplified Implementation Scheme for Space Vector Pulse Width Modulation of <italic>n</italic>-Level Inverter With Online Computation of Optimal Switching Pulse Durations

Space vector modulation (SVM) control of multilevel inverters (MLIs) is very popular. However, it gets extremely challenging with the increase in the number of output voltage levels due to the emergence of subtriangles in the various sectors of the hexagon, which results in increased computational complexity and storage requirements of switching states and corresponding pulse durations. Currently, this is handled through laborios offline computations in conjunction with the visual inspection of the space vector hexagon and its various sectors. This paper aims to simplify the implementation of the SVM scheme for an n -level MLI by proposing generalized equations that not only facilitate direct online computation of control pulses and obviate the requirement of lookup tables but also result in optimized switching. Yet, the on-time computations of the various MLI switches are still based on simple two-dimensional Cartesian co-ordinate system combined with the basic two-level inverter implementation. The proposed scheme makes use of a unique l-factor approach, which directly identifies the location of the various subtriangles in the space vector hexagon and leads to direct online computations of the control pulses. The proposed scheme is validated by simulations and experimental results for three- and five-level diode clamped MLI.

Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy

The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes.

Vector selection approach‐based hexagonal hysteresis space vector current controller for a three phase diode clamped MLI with capacitor voltage balancing

The purpose of this study is to provide a broad idea about current control scheme and equilibrating voltages in DC-link capacitors of the neutral-point clamped multilevel inverter (NPC-MLI), using an innovative hexagonal space vector hysteresis current control (SVHCC) scheme. The main ideology is to force the literal current vector to reach the reference current vector through an appropriate voltage vector selection sequence. This proposed scheme defines two hexagonal hysteresis bands encompassing the error vector, as a first step. With respect to the error vector location, the selection of the adjacent vector is acted to minimise the error vector. In addition to the error vector selection, the capacitor voltage is also equilibrated by controlling the degree of freedom available in selecting the switching vectors. The SVHCC scheme is intelligent in performing modulation depth dependent selection of switching vectors between the groups namely closest three vector and preferred three vector (PTV). This scheme balances the DC-link capacitors’ voltages within a tolerance limit for any value of modulation index. The proposed scheme is asserted through MATLAB/Simulink software. The superiority of the proposed technique is validated through the 2 kW NPC-MLI supported with SPARTAN III 3AN –XC3S400 field programmable gate array.

Comparison of Three, Five and Seven Levels Diode Clamped Multilevel Inverter Topologies based Shunt Hybrid Active Power Filter for Harmonics Compensation with Equal DC Link

The multilevel inverter is coming out as a new type of power inverter choice for high power applications. This type of inverter can constitute high voltage and decrease harmonics by its own circuit topology. This paper presents comparison of three, five and seven levels diode clamped multilevel inverter (DCMLI) topologies based shunt hybrid active power filter for harmonics mitigation of the nonlinear loads. The compensation process is based on synchronous reference frame method. Theoretical analyses and simulation results are obtained from an actual industrial network model in PSCAD. The simulation results are presented for a proposed system in order to demonstrate that the harmonic compensation performance meets the IEEE-519 standard.

Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor

This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.

On design and implementation of three phase three level shunt active power filter for harmonic reduction using synchronous reference frame theory

Shunt active power filter is commonly used to eliminate current harmonics generated in the source side due to presence of non-linear loads. This scheme consists of three phase three level diode clamped multilevel inverter and a DC capacitor that act as a shunt active power filter to mitigate the supply current harmonics and inject the required reactive power to non-linear loads. In this paper, using synchronous reference frame algorithm, a three phase three level SAPF is implemented on an embedded platform. In SRF theory, reference signals are transformed from a–b–c stationary frame to 0–d–q rotating frame. The reference signals in the 0–d–q rotating frame are controlled to get the desired reference signals using PI controller. The PWM signal generation for the three phase three level inverter is computed directly from the sampled amplitudes of the reference phase voltages. The practical implementation of the SAPF is realized using Xilinx XC3SD1800A – FG676-4 Spartan 3A DSP FPGA controller. This system is simulated using MATLAB/SIMULINK and the simulation results are compared with prototype hardware model for validating the effectiveness of the proposed system. Based on the studies, it is concluded that the SAPF is easy for implementation for reducing the Total Harmonic Distortion below 5% as per IEEE-519 standard.

Improved SVPWM vector selection approaches in OVM region to reduce common-mode voltage for three-level neutral point clamped inverter

Abstract Multilevel inverters (MLIs) have an essential portion in industrial applications. Eventhough there are various elementary developments in MLI and its pulse width modulation (PWM) control strategies, unfortunately those strategies are least bothered about the common mode voltage (CMV). The CMV appears at the neutral point of the motor’s star connected stator windings with respect to the source ground. This study proposes PWM schemes for three level diode clamped multilevel inverter (DC-MLI) which use an unpretentious switching sequence to determine the triangle for maximum output voltage and minimum CMV in entire modulation range. Here two types of approaches are proposed: (i) Partial elimination SVPWM (PE-SVPWM) and (ii) Full elimination (FE-SVPWM). The proposed strategies suggest switching selection by using the control degree of freedom available in SVPWM without affecting the inverter output voltage. As a result, CMV reduction and elimination with maximum output voltage and better THD is achieved. The proposed PWM approaches can be extended for any number of levels. The theoretical study, the MATLAB/Simulink software based computer simulation and Field Programmable Gate Array (FPGA) SPARTAN-III-3AN-XC3S400 processor supported hardware corroboration have shown the superiority of the proposed technique over the existing SVPWM schemes.

A Novel Multilevel Inverter Circuit for the Performance Enhancement of Direct Torque Controlled Induction Motor

Induction motor is the most sought after motor in the industry for excellent performance characteristics and robustness. Developments in the Power Electronic circuitry have revolutionised the induction motor industry leading to the developments in various control strategies and circuits for motor control. Direct Torque Control (DTC) is one of the excellent control strategies preferred by industries for controlling the torque and flux in an induction machine. The main drawback of DTC is the presence of torque ripple which is slightly more than the acceptable limit. There are various parameters that introduce ripples in the electromagnetic torque, one of them being the type of inverter circuit. There are various types of inverter circuits available and the effect of each of them in the production of torque ripple is different. This work is an attempt to identify the influence of various multilevel inverter circuits on the torque ripple level and to propose the best inverter circuit. The influence of multilevel diode clamped inverter and cascaded H bridge inverter circuits on torque ripple minimization, is analysed using simulation studies for identifying the most suitable multilevel inverter circuit which gives minimum torque ripple. The results obtained from the simulation studies are validated by hardware implementation on 0.75 kW induction motor.

Simulation Analysis of Three Level Diode Clamped Multilevel Inverter Fed PMSM Drive Using Carrier Based Space Vector Pulse Width Modulation (CB-SVPWM)

This paper proposes implementation of Three Level Diode-Clamped Multilevel inverter using IGBT's fed PMSM drive. The pulses for the inverters have been developed by using Carrier based Space Vector Pulse Width Modulation Technique (CB-SVPWM). Carrier based Space Vector Pulse Width Modulation Technique is most prominent PWM technique for three phase voltage source inverters for the control of Permanent Magnet Synchronous Motors. The output voltages, currents, torque & speed characteristics have studied for three-level inverters fed PMSM drive. It has observed three -level inverter with Carrier based Space Vector Pulse Width Modulation Technique (CB-SVPWM) can use more DC link voltage as compare to Space Vector Pulse Width Modulation Technique (SVPWM). and also CB-SVPWM Technique utilizes DC bus voltage more efficiently and generates less harmonics.

Power Control in Grid-Connected Wind Energy System Using Diode-Clamped Multilevel Inverter

ABSTRACTThis paper presents dynamic modelling and control of real and reactive power in grid-connected variable speed wind energy conversion system using diode-clamped multilevel inverter (DCMLI). A modified five-level DCMLI is used for power control, which eliminates the requirement of transformer and improves the quality of controlled output voltage. It is shown that the system is dynamically stable and is able to control the real and reactive power independently, and provides harmonic compensation within standard limits. The voltage balancing across the capacitors of the five-level diode-clamped inverter is obtained using external balancing circuits. The performance of the proposed control method is tested under variable wind speed, sudden load changes, and under single-phase and three-phase faults. Simulation studies PSCAD/EMTDC verifies the proposed control method.

A Closed Loop Current Control of PV-Wind Hybrid Source Fed Grid Connected Transformerless Diode Clamped-Multi Level Inverter

This paper presents a closed loop grid current control of Solar PV-Wind hybrid source fed split inductor based DC-MLI. Renewable energy sources generate significant proportion of global energy demand and will be the focal point of power generation by the turn of a few decades. Hybrid systems integrate the standalone efficiencies of PV and Wind generation to complement and reinforce individual output. A Diode Clamped or Neutral Point Clamped three level inverter reduces switching stresses and is apt for medium voltage high power applications. Space Vector PWM control of inverter reduces harmonic distortion besides eliminating neutral point fluctuation, capacitor balancing problem and common mode voltage reduction. It provides switching states for the inverter based on location of a space vector using reference voltage from grid. Using closed loop control the total harmonic distortion in grid current was reduced. The simulation and experimental results of the proposed renewable hybrid system were verified using Matlab/Simulink and FPGA.

English

Selective harmonic elimination pulse width modulation (SHEPWM) technique is applied to diode clamped multi-level inverter (DCMLI) to reduce total harmonic distortion (THD) and improve the quality of output power. The modulation technique is implemented centered on dog leg optimization method to find the optimized values for switching angles (θ) of switches (IGBTs) employed. Twelve level diode clamped inverter is implemented in Matlab and the results are compared with non-optimized switching angles also 5-level DCMLI using SHEPWM is compared with other modulation techniques.

Comparative Analysis of Harmonic Distortion of a Solar PV Fed Cascaded H-bridge Multilevel Inverter Controlled by FPGA and Diode Clamped Inverter

Background/Objectives: Multilevel Inverters are growing technology, even there are many topologies available in real world, here new multilevel topologies such as diode clamped multilevel inverter and cascaded-H-bridge inverter are discussed and comparative results for lower total harmonic distortion are analysed. Methods/Statistical Analysis: Neutral point diode clamped inverter is analysed and its total harmonic distortion value is calculated. Cascaded H-Bridge (CHB) 7 level inverter is analysed and then simulated, finally it is verified using FPGA controller. Three H-bridges are seriously connected to produce 7 level output voltage, FPGA controller uses Sinusoidal Pulse Width Modulation (SPWM) to produce pulse pattern for H-bridges. Results: This topology is tested in Matlab/Simulink environment. Total Harmonic Distortion (T.H.D) value of 7 level voltages is seen as a 30.33%. Which is very low as compared with 3 phase diode clamped five level inverter (81.7%). Conclusion/Application: Solar Photo Voltaic system is employed to compete the disadvantages of conventional energy sources and resulted in energy conservation system that reduces power consumption.

Voltage balancing technique in a space vector modulated 5‐level multiple‐pole multilevel diode clamped inverter

Unbalanced voltage across the dc-link capacitors of classical diode clamped multilevel inverters (DCMI) generates lower order harmonics in the output voltage and increases the voltage stress on the switching devices which may result in permanent damage to the switching devices. This study proposes a space vector modulation (SVM) based voltage balancing strategy for a new 5-level multiple-pole multilevel diode-clamped inverter (M2DCI) topology to eliminate the voltage drift phenomena. The 5-level M2DCI topology which is derived from 3-level DCMI topology uses lesser number of clamping diodes compared with the conventional 5-level DCMI topology. An effective switching function model of a new multilevel inverter is derived and is used for dc-link capacitor voltage control. The method utilises the redundant vector property to balance the dc-link capacitor voltages without using any auxiliary hardware. The dependence of the capacitor voltage variation on the load power factor and modulation index has been extensively studied for 5-level M2DCI. The range of operation for the new topology with the proposed control strategy is also presented based on the simulation studies in the Matlab/Simulink® and PSIM environment and verified using experimental results.

Multi‐resolution analysis for converter switch faults identification

Multilevel inverters (MLI) are extensively used in various fields and industrial applications. This study proposes a simple algorithm for detection and identification of switch faults in insulated gate bipolar transistors (IGBTs) of multilevel inverter feeding an induction motor drive. The effects on the system for switch shorted are more severe than the switch opened if no protective action is taken in time. A fast and novel fault identifier designed in this study is used not only for switch short fault but also for switch open fault by analysing the performance of MLI drive system using wavelet based multi-resolution analysis (MRA). On occurrence of switch fault in inverter, the fault information appears in the signals in frequency region resulting in variation in the details of level of wavelet transform (WT). The instant of variation in the WT is correlated with the instant of fault. The voltage and current signals from the experimental setup were used as input for wavelet analysis to develop suitable feature vector that will act as signature to discriminate faulty system from healthy one. The experimental prototype of five level diode clamped multilevel inverter feeding an induction motor has been implemented to validate the fault analysis with simulated result.