Dimensional Packaging Research Articles

Study on the 12 in. wafer uniformity of high aspect ratio TSV filling by using rotation cathode

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained.

Exceptional preservation of three-dimensional dunes on an ancient deep-marine seafloor: implications for sedimentary processes and depositional environments

Depositional and erosional bedforms can be used to reconstruct sedimentary processes and aid palaeoenvironmental interpretations. Using exhumed deep-marine strata in the Eocene Aínsa Basin, Spain, we document a 3-dimensional package of dunes, a rarely identified bedform in deep-marine environments. Our analysis shows that the dunes have curvilinear crests in planform, with smaller superimposed oblique dunes and ripples across the stoss sides. Beds containing these dunes have two main internal divisions: a lower inversely-graded (fine-to-coarse sandstone) and predominantly structureless division, and an upper coarse-grained sandstone division with well-developed cross-stratification, which is scoured and mantled with mudclasts and coarse-grains on the stoss-side. The rugose remnant relief of the bedforms controls the location of subsequent bedforms. Following recently reported direct measurements of natural turbidity currents, we interpret the basal division as recording deposition from the dense basal head of a high-velocity turbidity current, followed by the development of dunes beneath the more sustained but relatively high-velocity and unsteady flow body that reworked the initial sandy deposit into downstream migrating dunes and scours. These dune-forming beds have been identified in different deep-water environments in the Aínsa Basin stratigraphy, including channel overbank and channel mouth settings and scour-fills. These locations suggest that the dunes were intimately tied to high-velocity flows that bypassed through channel axes before expanded and depositing in less confined channel overbank or channel mouth settings. Preservation of these dunes in the Aínsa Basin was likely enhanced by tectonically-forced lateral migration of channels, which prevented cannibalisation of bypass-zones, in combination with high aggradation rates due to confinement, or periodic supply of flows from a particularly clay-poor source area. Where identified these dune-like bedforms are considered diagnostic of substantial sediment bypass downslope to deep-water basins.

Self-alignment of whole wafers using patterning for capillary forces

Three dimensional packaging schemes take advantage of multiple substrate materials, functionality, and reduced area constraints. Alignment of stacks of wafers becomes difficult as the number increases. We investigate full-wafer self-alignment as a means for solving this problem. To date, capillary self-alignment has only been accomplished with tiny, millimeter-sale, objects. Here, wafer-level self-alignment is demonstrated with capillary alignment forces, and we describe several needed, nontrivial advances and considerations compared to the chip alignment. The patterning scheme and the alignment force character are found to be crucial to ensure alignment at the wafer scale. Avoidance of alignment at local minima with the use of multiple length scales, prevention of upper wafer dragging by balancing the wafer and using engineered flow channels, and increased pattern features at small misalignments to combat the decreased alignment force are all discussed. A capture range of a few millimeters in position and several degrees in rotation for the self-alignment is achieved by patterning a hydrophobic self-assembled monolayer. These advances for large structure self-alignment offer a path forward for self-assembly of wafer stacks or other complex, large structures useful for mmWave, 5G antennas, for example. The scheme is compatible with a bonding scheme using the bonding precursor as the alignment fluid.

The demonstration of low-temperature (350 °C) grown carbon nano-tubes for the applications of through silicon via in 3D stacking and power-via

Low temperature Carbon Nano-tubes (CNTs) growth technology is developed in this work with the insert of Al (Aluminum) between Ni (Nickel) and Ti (Titanium) as the reactant. The optimized Al thicknesses are also investigated. CNTs growth at the low temperature below 400 °C is the key factor for the back end of line compatible process integration. In this work, we grow the CNTs by thermal chemical vapor deposition process at 350 and 400 °C. The low ratio of peak ID/IG in Raman spectra and scanning electron microscope images proves the CNTs material quality. On the other hand, the high thermal conductivity (k) value of ∼50 W m − 1 K − 1 is also demonstrated. Both high material quality and k value on our low temperature grown CNTs show promising opportunities for the integration of semiconductor three dimensional packages and power-via related applications.

Three-Dimesnional Semicondoctor Stacking using TSV(Through-Si-Via) Technology

Recently, the electronics industry is developing toward artificial intelligence, the Internet of things, fifth-generation technology, and high-performance computing. High-density electronics packaging, high speed, high performance, and miniaturized size are required to satisfy these trends. Three-dimensional Si-chip stacking using through-Si via (TSV) has attracted the attention of industries related to these requirements. In this study, TSV fabrication using the deep reactive ion-etching process and the coating of functional layers on the TSV wall, such as insulating, adhesion, and seed layers, were investigated. In addition, Cu electroplating in the TSV was analyzed in detail. The solutions to other accompanied technical barriers for packaging high-density electronics can improve smartness and con- venience. Key words: Three dimensional packaging, Through-Si-Via, Functional layers, Electroplating

Toward Practical-Scale Quantum Annealing Machine for Prime Factoring

We propose a prime factorizer operated in a framework of quantum annealing (QA). The idea is inverse operation of a multiplier implemented with QA-based Boolean logic circuits. We designed the QA machine on an application-specific-annealing-computing architecture which efficiently increases available hardware budgets at the cost of restricted functionality. The invertible operation of QA logic gates consisting of superconducting flux qubits was confirmed by circuit simulation with classical noise sources. The circuits were implemented and fabricated by using superconducting integrated circuit technologies with Nb/AlOx/Nb Josephson junctions. We also propose a 2.5Dimensional packaging scheme of a qubit-chip/interpose /package-substrate structure for realizing practically large-scale QA systems.

Ataktogamous green microalgae of the genus Chlorosarcinopsis Herndon (Chlorophyceae, Chlorophyta) from Zabaikalskiy region (Russia)

The algae described in this paper appeared in enrichment culture from epiphytic mosses sample collected in southern Zabaikalie (Russia). This organism forms 2–8-celled and 3-dimensional packages of irregular shape. Vegetative cells are spherical, ellipsoidal and ovoid when solitary; cells with thin wall, thickening with age and occasionally with a unipolar manner. The cells and packages are devoid of a gelatinous matrix. There are akinete-like cells with sculptured cell wall. Sexual reproduction is ataktogamic. The results of morphologic and molecular phylogenetic studies allow us to attribute the alga to the genus Chlorosarcinopsis and show a high similarity with C. dissociata and C. bastropiensis. However, obtained data do not prove its identity to any known species of the genus.

The Protective Effect of Middle Cerebral Artery Calcification on Symptomatic Middle Cerebral Artery Infarction.

The presence of intracranial artery calcification is associated with an increased risk for stroke. However, calcified atherosclerotic plaques are also known to be less vulnerable to rupture. Given this discrepancy, we investigated whether the vulnerability of intracranial arterial atherosclerosis differed based on the presence or absence of calcification. We considered consecutive patients with acute stroke in the unilateral middle cerebral artery (MCA) territory. Patients with any stenotic MCAs were included in this study. Symptomatic MCA was defined as the occurrence of infarctions relevant to the stenotic MCA. The presence of calcification in the MCA was evaluated on noncontrast thin-section computed tomography images using a 3dimensional software package. Generalized estimating equations were used to compare the frequency of calcification between symptomatic and asymptomatic stenosis. Of the 1066 MCAs examined in 533 patients, 645 MCAs were stenotic and were included in the study. Among the 645 stenotic MCAs, 406 MCAs (62.9%) were symptomatic. Calcification was observed in 36 MCAs (5.6%). Calcification in the MCA was more frequently observed in the asymptomatic group (7.9% versus 4.2%; P=0.032). On multivariable analysis, the presence of calcification in MCA atherosclerosis was less frequent in the symptomatic group (odds ratio, 0.46; 95% confidence interval, 0.23-0.92; P=0.027). This study showed that calcified atherosclerosis in the MCA was less frequently symptomatic.

A theoretical study to improve wire sag of ultra-long wire bond loops for 3D/MCM packaging

An innovative theoretical model by altering cross section of gold wire is proposed to reinforce the wire sag stiffness of a wire bond that suffered low yield for the applications of 3-dimensional and multi-chip module (MCM) packaging. The flexural rigidity of a wire bond is found to be a function of the material properties in the moment of inertia of a bond wire. Suffice to say, if the moment of inertia of the bond wire can be raised, the associated sag deflection will be diminished. By manipulating the moment of inertia of the bond wire, the sag deflection of the wire bond can be regulated appropriately to avoid wire sag and even the wire sweep enigma. The ellipse-like cross section of a wire bond is applied as a numerical example to improve the wire sweep stiffness or wire sag stiffness in this study. The results show the sag deflection of a wire bond can be reduced significantly if the ellipse-like cross section is oriented in the preferred direction of flexural rigidity of a wire bond. Furthermore, a systematic study of matching design is performed to control wire sag and wire sweep for the wire bonding applications of overhang cross-stacked and step-stacked packaging. It shows that to use a single diameter of bonding wire in these complicate bonding environments of overhang stacked configurations is a favored possibility. The advantages shown from the theoretical study need to be implemented in further work in a production environment on current wire bonding equipment.

Transient Liquid Phase Sintering Pastes in Heterogeneous Integration

Integrated package technologies continue to be the dominant trend in the electronics packaging industry. In particular, heterogeneous integration of logic and memory or sensing is an enormous growth segment for both mobile electronics and IoT applications. In the mobile microprocessor segment of the field, the most advanced technologies will be implemented in the early adopter class. New package architectures and interconnect schemes will be vetted and implemented without significant cost pressure, performance is the driver. In the IoT segment and downstream mobile, however; lower cost alternatives to cutting edge packaging architectures are needed to drive market growth. Sintering pastes offer an opportunity to cost-effectively enable cutting edge 3D package capability for a wider variety of applications. In this paper we will explore the use of transient liquid phase sintering (TLPS) pastes in package-on-package (POP) schemes for integrated logic with memory or sensing functions in through mold via architectures. Through mold via technology has been well established in the industry and has significantly contributed to the adoption of three dimensional packaging architectures. The advantages of using TLPS pastes in similar structures will be detailed.

지역브랜드 마케팅을 위한 캐릭터패키지 디자인 연구 -전주비빔밥 응용 패스트푸드 '믹스밥' 패키지 개발을 중심으로

기술과 품질의 차이가 하루가 다르게 좁혀지고 있는 현대의 자유시장경제하에서 제품의 차별화를 위한 마케팅 전략은 더욱더 격화되는 디자인 경쟁에 의해 좌우되고 있다. 그 중에서도 제품의 외형을 통해 소비자에게 시각적으로 닿게 되는 패키지디자인은 가격이나 기능에 앞서 브랜드이미지에 영향을 미치는 직접적 커뮤니케이션이다. 패키지디자인은 제품을 포장, 운반, 보관하고 적재하는 기본 기능만이 아니라 효과적인 비주얼 이미지로 소구력을 높여 브랜드이미지를 각인시키고 구매결정을 이끈다. 최근의 패키지디자인은 캐릭터를 적극 활용하고 있는데 단지 캐릭터의 이미지만을 사용하는 것이 아니라 캐릭터의 형태가 패키지의 물적 구조와 융합된 입체적인 디자인으로 2차적 재미와 효과를 주고 있다. 이렇게 캐릭터를 잘 활용한 패키지디자인은 그 자체로 강력한 마케팅 수단이자 가치 있는 디자인 자산이며, 캐릭터를 활용하는 방식에 따라 그 부가가치는 더욱 증대될 수 있다. 위트 있는 아이디어로 판매 뿐 아니라 브랜드이미지 향상에 기여하는 캐릭터패키지는 대기업 뿐 아니라 다양한 제품군에서 효과적으로 사용할 수 있는 마케팅수단이다. 특히 지역단위를 넘어선 판매와 홍보에 절실한 지자체별 관광상품에 잘 활용한다면 단지 구매동기만을 유발시킬 뿐 아니라 패키지 자체가 관광자원이 되는 일석이조의 효과를 누릴 수 있다. 본 연구는 그 실례로 전북 전주의 한 지역브랜드를 마케팅하는 수단으로써 캐릭터패키지를 제안하여, 자체캐릭터를 개발하고 이를 패키지의 입체적 형태로 디자인하는 캐릭터패키지를 기획, 제작하였다. 그리고 이런 일련의 과정을 통해, 기존 브랜드의 이미지를 재정립하거나 강화하기 위한 브랜드마케팅 전략으로서의 패키지디자인을 제시하고자 한다. Design is a fatal factor to differentiate and survive one product from the other in fierce competition of the market, when other conditions such as price or quality makes no much difference. Among many marketing tools, package design is known as a direct communication that visualizes and forms the very initial brand image of a product. Package design is not only for packing, transporting, storing and loading but for engraving the brand image in a consumers' mind and lead them to purchasing. One of recent package design trands is various ways of using character, not just as a printed image on the surface but as a part of three dimensional structure of package. If it succeed, the package design could give out the secondary fun and impact to the consumers. The package design with an effective character is itself a great marketing tool and valuable design asset, which can bring a further profit to the company. Especially, character-package can be a powerful and effective marketing method for various local products, in needs of further publication and sales with limited cost. It should motivate the sales of the products by grabbing their attention and taken as a souvenir. This research takes a character package as a useful marketing method for a local brand in Jeonju, South Korea, and tries to design a three dimensional package using its own character. Through the process, the research aims to propose an important design strategy for repositioning or enhancing an existing brand.

구리 전해 도금을 이용한 실리콘 관통 비아 채움 공정

반도체 배선 미세화에 의한 한계를 극복하기 위해 실리콘 관통 비아(through silicon via, TSV)를 사용한 소자의 3차원 적층에 대한 연구가 진행되고 있다. TSV 내부는 전해도금을 통해 구리로 채우며, 소자의 신뢰성을 확보하기 위해 결함 없는 TSV의 채움이 요구된다. TSV 입구와 벽면에서는 구리 전착을 억제하고, TSV 바닥에서 선택적으로 구리 전착을 유도하는 바닥 차오름을 통해 무결함 채움이 가능하다. 전해 도금액에 포함되는 유기 첨가제는 TSV 위치에 따라 국부적으로 구리 전착 속도를 결정하여 무결함 채움을 가능하게 한다. TSV의 채움 메커니즘은 첨가제의 거동에 기반하여 규명되므로 첨가제의 특성을 이해하는 연구가 선행되어야 한다. 본 총설에서는 첨가제의 작용기작을 바탕으로 하는 다양한 채움 메커니즘, TSV 채움 효율을 개선하기 위한 평탄제의 개발과 3-첨가제 시스템에서의 연구, 첨가제 작용기와 도금 방법의 수정을 통한 채움 특성의 향상에 관한 연구를 소개한다. Intensive researches have been focused on the 3-dimensional packaging technology using through silicon via (TSV) to overcome the limitation in Cu interconnection scaling. Void-free filling of TSV by the Cu electrodeposition is required for the fabrication of reliable electronic devices. It is generally known that sufficient inhibition on the top and the sidewall of TSV, accompanying the selective Cu deposition on the bottom, enables the void-free bottom-up filling. Organic additives contained in the electrolyte locally determine the deposition rate of Cu inside the TSV. Investigation on the additive chemistry is essential for understanding the filling mechanisms of TSV based on the effects of additives in the Cu electrodeposition process. In this review, we introduce various filling mechanisms suggested by analyzing the additives effect, research on the three-additive system containing new levelers synthesized to increase efficiency of the filling process, and methods to improve the filling performance by modifying the functional groups of the additives or deposition mode.

The Influences of Iodide Ion on Cu Electrodeposition and TSV Filling

Through silicon via (TSV) technology has been researched for 3-dimensional packaging of electronic devices, and Cu electrodeposition has been used for TSV filling. The organic additives are one of the most important factors in Cu electrodeposition affecting Cu gap-filling, and the leveler usually plays a decisive role. In this research, iodide ion (I−) is adopted instead of organic leveler for Cu bottom-up filling. The behaviors of I− are investigated by various types of electrochemical analyses. Especially, the influences of I− on the adsorption of the accelerator and suppressor are extensively studied, and it is confirmed that I− makes the suppression layer robust while reducing the adsorption of the accelerator. Also, it was observed that the effect of I− is greater under the strong convection of electrolytes than without convection, meaning that I− could induce selective deposition at the bottom of the features. Based on this, TSV-scaled trenches are successfully filled by potentiostatic Cu electrodeposition in the presence of the accelerator, suppressor, and I− without any organic levelers.

The Simple Analytics of Job Displacement Insurance

Job displacement in the U.S. is a serious threat to the earnings of long-tenured workers, through both (i) unemployment spells and (ii) reduced reemployment wages. Although full insurance requires both unemployment benefits and wage insurance, supply difficulties limit actual-loss insurance, and separation packages typically include partial unemployment insurance and scheduled (fixed sum) severance pay. The design of this two dimensional package requires a systems approach as well as a generalized replacement ratio measure of adequacy). Job search moral hazard and layoff moral hazard (firing costs), individually and in combination, introduce potentially serious contracting concerns. Economic theory provides a practical guide to the integration of these insurance instruments in this complex planning environment. One important implication: given the structure of earnings losses at displacement in the U.S., severance pay should increase with length of service in the firm (tenure), which is common, and unemployment insurance benefit levels should fall, which is not.

3차원 실장을 위한 TSV의 Cu 전해도금 및 로우알파 솔더 범핑

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

A Review of Failure Analysis Methods for Advanced 3D Microelectronic Packages

Advanced three dimensional (3D) packaging is a key enabler in driving form factor reduction, performance benefits, and package cost reduction, especially in the fast paced mobility and ultraportable consumer electronics segments. The high level of functional integration and the complex package architecture pose a significant challenge for conventional fault isolation (FI) and failure analysis (FA) methods. Innovative FI/FA tools and techniques are required to tackle the technical and throughput challenges. In this paper, the applications of FI and FA techniques such as Electro Optic Terahertz Pulse Reflectometry, 3D x-ray computed tomography, lock-in thermography, and novel physical sample preparation methods to 3D packages with package on package and stacked die with through silicon via configurations are reviewed, along with the key FI and FA challenges.

Effect of Joint Scale and Processing on the Fracture of Sn-3Ag-0.5Cu Solder Joints: Application to Micro-bumps in 3D Packages

In 3-dimensional (3D) packages, a stack of dies is vertically connected to each other using through-silicon vias and very thin solder micro-bumps. The thinness of the micro-bumps results in joints with a very high volumetric proportion of intermetallic compounds (IMCs), rendering them much more brittle compared to conventional joints. Because of this, the reliability of micro-bumps, and the dependence thereof on the proportion of IMC in the joint, is of substantial concern. In this paper, the growth kinetics of IMCs in thin Sn-3Ag-0.5Cu joints attached to Cu substrates were analyzed, and empirical kinetic laws for the growth of Cu6Sn5 and Cu3Sn in thin joints were obtained. Modified compact mixed mode fracture mechanics samples, with adhesive solder joints between massive Cu substrates, having similar thickness and IMC content as actual micro-bumps, were produced. The effects of IMC proportion and strain rate on fracture toughness and mechanisms were investigated. It was found that the fracture toughness GC decreased with decreasing joint thickness (hJoint). In addition, the fracture toughness decreased with increasing strain rate. Aging also promoted alternation of the crack path between the two joint–substrate interfaces, possibly proffering a mechanism to enhance fracture toughness.

Galvanostatic bottom-up filling of TSV-like trenches: Choline-based leveler containing two quaternary ammoniums

Through Silicon Via (TSV) technology is essential to accomplish 3-dimensional packaging of electronics. Hence, more reliable and faster TSV filling by Cu electrodeposition is required. Our approach to improve Cu gap-filling in TSV is based on the development of new organic additives for feature filling. Here, we introduce our achievements from the synthesis of choline-based leveler to the feature filling using a synthesized leveler. The choline-based leveler, which includes two quaternary ammoniums at both ends of the molecule, is synthesized from glutaric acid. The characteristics of the choline-based additive are examined by the electrochemical analyses, and it is confirmed that the choline-based leveler shows a convection dependent adsorption behavior, which is essential for leveling. The interactions between the polymeric suppressor, accelerator, and the choline-based leveler are also investigated by changing the convection condition. Using the combination of suppressor, accelerator, and the choline-based leveler, the extreme bottom-up filling of Cu at trenches with dimensions similar to TSV are fulfilled. The mechanism of Cu gap-filling is demonstrated based on the results of electrochemical analyses and feature filling.

Electro- and thermomigration induced Cu3Sn and Cu6Sn5 formation in SnAg3.0Cu0.5 bumps

Two important trends in the microelectronics business are the development of three dimensional packaging solutions which increase the number electronics components on the same area, and the application of VLSI electronics under harsh environment conditions. Both trends lead to a growing importance of intermetallic compound (IMC) formation in Sn based solder joints. Due to miniaturization a growing part of the solder joint volume is transformed into IMCs and finally the reflow process becomes a transient liquid phase soldering (TLPS) process. For harsh environment applications TLPS enables the transformation of low melting Sn contacts into high melting IMC joints. In both cases a model for the prediction of migration-induced IMC formation is required for the fabrication of IMC joints.For the general prediction of the migration induced IMC formation the related material parameters are needed. Against this background the Cu3Sn and Cu6Sn5 formation was observed during temperature storage tests on Amkor® Package-on-Package packages (12×12mm) with SnAg3.0Cu0.5 ball grid arrays. A mathematical model was developed to calculate the average mass flux of Sn and Cu during the stress tests. Based on the mass flux values the activation energies and diffusion constants for Cu and Sn in Cu3Sn and Cu6Sn5 were determined. Afterwards the temperature storage was combined with an AC and a DC current load to investigate thermo- and electromigration-related phenomena. Based on the IMC formation speed during the AC and the DC tests the heat of transport Q* and the effective charge of the moving ion Z* were calculated. An interpretation of the material parameters is given in consideration of the high defect density in Cu3Sn and Cu6Sn5.

Pre-applied Inter Chip Fill for 3D-IC Joining

For the conventional two dimensional (2D) packaging of integrated circuit (IC), reflow and capillary under fill have been used for more than a decade. But for the purpose of low power and high performance of IC, three dimensional IC (3D-IC) have been proposed in recent years. In case of 3D-IC, both bump pitches and gaps between stacked thin chips should be fine and narrow, so that pre-applied inter chip fill (ICF) which is applied in thermal compression bonding have been proposed. In this process, not only low viscosity but also thermal conductivity is simultaneously required. In this study, some of selected epoxy based matrix and filler were simulated and evaluated for pre-applied ICF, we confirmed its process applicability to pre-applied chip bonding. Physical characteristics of cured ICF and void-less joining were also discussed.