Digital Signal Processing Research Articles

Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing

This work presents a novel approach to improve the area and energy efficiency of 5:3 counter, a key element used in digital arithmetic. To provide an effective substitute for addition operations, mostly in the partial product reduction stage of larger multipliers, this study suggests a new 5:3 counter. The Input Shuffling Unit (ISU) is employed within the proposed 5:3 counter to minimize gate-level implementation and path delay during partial product reduction in 16-bit and larger multipliers, thereby enhancing area and energy efficiency. Consequently, there are 84% fewer choices of input-output combinations, thereby decreasing the circuit complexity with respect to area and energy usage. When compared to its existing counterparts, the suggested 5:3 compressor improves area utilization and energy usage by an average of 11%, 17%, and 17% in 8-, 16-, and 32-bit multipliers, respectively. The results of simulations demonstrate the superiority of our method over traditional designs, providing an increase in both area and energy efficiency. These results highlight the applicability and scalability of our method, which is appropriate for a variety of applications such as embedded systems and digital signal processing.

Design and Simulation of Vedic Multiplier Using Verilog HDL

Abstract: This Paper is created for the simulation of a high speed Vedic multiplier. In the proposed paper, the multiplier circuit is designed by using algorithms that involve Vedic Mathematics. Calculations that involve Vedic mathematics are derived from the old contexts known as Vedas. The VHDL programs are synthesized and simulated using Xilinx ISE simulator. The study of Vedic multipliers is done in comparison with the conventional multipliers to find the fact that which multiplier is fast and efficient and the research and analysis has shown that the Vedic multiplier is more efficient than conventional multipliers because of its fast response in digital signal processing and it gives less delay in system logic design. Vedic mathematics used in the Vedic multiplier increases the speed of multiplier as it reduces the number of partial products. Hence, the speed of the overall digital design can be increased by implementing a Vedic multiplier.

Real-time FPGA prototyping of Doppler frequency shift compensation using DSP-assisted automatic frequency control.

This Letter presents a real-time coherent receiver using digital signal processing (DSP)-assisted automatic frequency control (AFC) to compensate for the Doppler frequency shift (DFS). DFS compensation range of ±8 GHz and the frequency shifting rate of 33 MHz/s are demonstrated in an FPGA-based 2.5 Gbaud QPSK coherent optical system. The experimental results indicate that the scheme achieves a sensitivity of -47 dBm at a bit error rate (BER) of 2E-4. The power penalty induced by the DFS compensation is less than 1 dB.

Assessing Student Performance in Digital Signal Processing (DSP) Subjects: A Comparative Study of Traditional and Online Learning Environments

Assessing Student Performance in Digital Signal Processing (DSP) Subjects: A Comparative Study of Traditional and Online Learning Environments

Разработка и исследование подхода к обработке сигналов цифровых измерительных трансформаторов тока и напряжения

During the development of secondary systems of stations and substations, including relay protection, automation, control, electricity metering, etc., qualitative changes have recently occurred due to the introduction of digital technologies. The introduction of digital technologies is supported by innovative development programs such as “Digital Transformation 2030”. The introduction of digital technologies is associated with the use of digital data transmission channels according to uniform standards. Projects of “digital substations” are being actively implemented with the transmission of digital information at all levels, including the primary equipment, the transmission of information both from current and voltage measuring transformers, and from switching devices. Currently, digital instrument transformers are actively being developed and implemented, in which information about measured currents and voltages is presented in digital code. New approaches to measure primary currents and voltages, and transmit information pose new challenges, and open prospects for improving signal processing methods used for relay protection purposes. Thus, the relevant aim of the study is the development and research of approaches to digital processing of signals of digital instrument current and voltage transformers. To solve the problems posed within the framework of this study, analytical and numerical solution methods have been used. Numerical methods are applied using software products such as MathCAD and the Python programming language to generate signals and display them on graphs. To substantiate the reliability, verification of the results obtained by different methods is carried out. The authors have formulated an approach to digital processing of signals obtained using current sensors of a digital instrument transformer. The authors have studied the approach to determine synchronized current vector values by processing information received from primary current converters. The characteristics of the algorithm for obtaining a vector have been analyzed and the dependences of errors on the influence of distorting factors have been plotted. The proposed approach is a development of the existing approach to obtain a vector by getting information from current sensors operating on different physical principles. The results show the advantages of the proposed method. The proposed digital signal processing algorithm is more technically expensive since it contains at least two metrologically calibrated measuring channels instead of one. However, all other things being equal, it allows to increase the accuracy and speed of the digital processing algorithms taken as a prototype. The results obtained can be used to formulate algorithms for measuring relay protection devices.

A Self‐Powered Smart White Cane for Improving Mobility of Visually Impaired Person Using a Triboelectric Nanogenerator

The present research offers an innovative approach to enhance the safety and mobility of people with visual impairments by using a smart white cane sensor. Herein, an aluminum electrode, Kapton film, and an inexpensive PET substrate are employed to develop an origami‐shaped multilayered triboelectric nanogenerator (TENG) device. The multilayered integration of three‐unit TENGs produces output with a high power of 51 μW at 50 MΩ, along with 155 V and 4.5 μA. Capacitor charging, low‐power electronics powering, and the integration of mechanoluminescent materials are demonstrated. The integration of mechanoluminescent materials enables efficient identification of visually impaired people in regions with poor lighting. A single‐electrode TENG is also implemented for successful surface material detection. To further enhance the sensor's capabilities, digital signal processing techniques are employed for obstacle recognition on their route. The intelligent white cane sensor effectively detects obstructions, offering the user instantaneous feedback and enabling more secure navigation in sophisticated environments. This study highlights the possibility of integrating TENG technologies to provide a complete solution for people with visual impairments. The smart white cane sensor has the potential to greatly increase the safety and independence of visually impaired people in a variety of outdoor and public spaces.

A hybrid ICEEMDAN and OMEDA-based vibrodiagnosis method for the bearing of rolling stock

Purpose. To develop a hybrid method based on ICEEMDAN and OMEDA for high-fidelity detection of the diagnostic features of the technical condition of roller bearing. Methodology. Due to digital signal processing the search was made of the informative components on the broadband spectra, envelope spectra, squared envelope spectra. The usage of the methods of mathematical statistics for the selection of informative IMFs as a result of iterative calculate procedures. The introduction of blind deconvolution method with a proper objective function for the enhancement of impulse fault features. Findings. The use of traditional spectral methods provided an incomplete list of diagnostic features of bearing roller damage. The empirical mode decomposition (EMD) method and its minor versions provide the series of intrinsic mode functions (IMFs). On the broadband vibration spectra of the selected low-frequency IMFs, diagnostic features were not detected in a sufficient number. Further research focused on the development of a hybrid method that takes into account the demodulation procedure of the high-frequency components of those IMFs that were selected according to the complex evaluation index. The Fast Kurtogram technique determined an informative frequency band of 7.2–7.5 kHz for demodulation and construction of the squared envelope spectra, where harmonics of the roller spin frequency and some side bands with a width equal to the separator rotation frequency appeared. The use of OMEDA caused the reduction of residual noise on the squared envelope spectra and bilateral sidebands to appear around all harmonics of the roller spin frequency. Originality. For the first time, the whole list of the diagnostic features of roller faults of the axle-box bearing was identified using the developed hybrid method, which involves steps of noise reduction for enhancing a physical meaning of a proper frequency components, associated with faults. The usage of the optimal minimum entropy deconvolution adjusted method helped to eliminate noise and provide all diagnostic features of the technical condition on the squared envelope spectrum. Practical value. The results of the study help to control the quality of repair of the axle-box rolling bearings on the test rig at the workshop of the freight railway car depot.

Chip-Based Electronic System for Quantum Key Distribution.

Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems.

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

Flexible and Reconfigurable OFDM Implementation in DSP Platform for Various Purposes and Applications.

In the modern technological era of sophisticated applications and high-quality communications, a platform of clever strategy and quickly updated systems is needed. It should be capable of withstanding the fastest emerging problems like signal attenuation and hostile actions intended to harm the whole network. The main contributions of this work are the production of an OFDM system (with low cost) that can sustain high-speed communications and be easily adjusted with new integrated code while exhibiting the feasibility of implementing a transmitter-receiver system in the same DSP and demonstrating the holistic approach with the qualitative integration of such an architecture in a warfare scenario. Specifically, in this research, the point of view is toward three facts. The first is to show a method of quick self-checking the operational status of a digital signal processor (DSP) platform and then the pedagogical issues of how to fast check and implement an updated code inside DSPs through simple schematics. The second point is to present the prototype system that can easily be programmed using a graphical user interface (GUI) and can change its properties (such as the transmitted modulated sinusoids-orthogonal frequency division multiplexing subcarriers). Alongside the presentation, the measurements are presented and discussed. These were acquired with the use of an oscilloscope and spectrum analyzer. The third point is to qualitatively show the application of such a system inside a modern warfare environment and to recommend various potential system responses according to the development of such a platform of reconfigurable implemented OFDM systems. The implementation was performed for two types of systems: (1) transmitter and (2) transmitter-receiver system. Notably, the system acts quickly with a delay of about 1 msec in the case of transmitting and receiving in the same DSP, suggesting excellent future results under real conditions.

Empowering high-dimensional optical fiber communications with integrated photonic processors

Mode-division multiplexing (MDM) in optical fibers enables multichannel capabilities for various applications, including data transmission, quantum networks, imaging, and sensing. However, high-dimensional optical fiber systems, usually necessity bulk-optics approaches for launching different orthogonal fiber modes into the optical fiber, and multiple-input multiple-output digital electronic signal processing at the receiver to undo the arbitrary mode scrambling introduced by coupling and transmission in a multi-mode fiber. Here we show that a high-dimensional optical fiber communication system can be implemented by a reconfigurable integrated photonic processor, featuring kernels of multichannel mode multiplexing transmitter and all-optical descrambling receiver. Effective mode management can be achieved through the configuration of the integrated optical mesh. Inter-chip MDM optical communications involving six spatial- and polarization modes was realized, despite the presence of unknown mode mixing and polarization rotation in the circular-core optical fiber. The proposed photonic integration approach holds promising prospects for future space-division multiplexing applications.

Digital Miniature Cathode Ray Magnetometer

In this study, we introduce the concept and construction of an innovative Digital Miniature Cathode Ray Magnetometer designed for the precise detection of magnetic fields. This device addresses several limitations inherent to magnetic probes such as D.C. offset, nonlinearity, temperature drift, sensor aging, and the need for frequent recalibration, while capable of operating in a wide range of magnetic fields. The core principle of this device involves the utilization of a charged particle beam as the sensitivity medium. The system leverages the interaction of an electron beam with a scintillator material, which then emits visible light that is captured by an imager. The emitted scintillation light is captured by a CMOS sensor. This sensor not only records the scintillation light but also accurately determines the position of the electron beam, providing invaluable spatial information crucial for magnetic field mapping. The key innovation lies in the combination of electron beam projection, CMOS imager scintillation-based detection, and digital image signal processing. By employing this synergy, the magnetometer achieves remarkable accuracy, sensitivity and dynamic range. The precise position registration enabled by the CMOS sensor further enhances the device’s utility in capturing complex magnetic field patterns, allowing for 2D field mapping. In this work, the optimization of the probe’s performance is tailored for applications related to the characterization of insertion devices in light sources, including undulators.

Mathematical Representation for speech signal based on ‎polynomial equation

The sound is an important vital information that it relies to recognize the character when lessening to it. Therefore, the audio signal adopted into many important applications. Sound forming and synthesizing in addition to distinguishing the speaker are so important in fields of digital signal processing. In this paper, work is done to represent acquired acoustic signal based on mathematical techniques. Mathematical representation provides deal with the sound signal which lead to smoothing, amplification or compression, in addition to the sound filtering process. In the proposed algorithm, polynomials of various degrees were adopted as a mathematical representation for speech signal, then the retrieved speech was studied based on level of clarity and the possibility of adopting it as an alternative signal in terms of the proximity to the original sound and the amount of noise added to it. The results shows that the proposed algorithm with degree of polynomial 20 and segment length 25 had the best sound representation and so closed to the original, which clearly seen from the evaluation parameters (Correlation=0.9993, Mean squared error(MSE) =1.32e-06, Standard deviation(STD)=1.80e-05 and the Euclidean dimension(ED) =0.1703).

Optimal speckle size and signal processing for displacement measurements using a 4f optical setup

Fully developed laser speckle patterns are, due to their high contrast and statistical nature, well suited to measure strain and displacement via an appropriately designed measurement system. Laser speckle patterns are formed when a sufficiently coherent light source, such as a HeNe-laser, illuminates an optically rough surface. Therefore, methods based on laser speckle patterns can be applied to any surface scatterer with a minimum mean surface roughness of about a quarter of the laser’s wavelength. This includes also materials such as thin natural and technical fibres as well as foils, for which the presented measurement system, including the digital signal processing, was designed. In order to achieve the best possible resolution of a speckle-based measurement system, combined with a sufficiently small measurement uncertainty, all available design parameters must be optimised. One of these parameters is the speckle size, which is dependant on the properties of the imaging optics. In this paper a subjective laser speckle-based measurement system based on a so-called 4f-optical setup is presented. This setup allows the speckle size to be controlled in both axial and lateral dimensions separately, which is achieved with the help of an aperture in the Fourier plane of the optics. It is shown that the optimal speckle size for the presented measurement system, not only depends on the physical setup, but also on the signal processing applied. The signal processing routine estimates displacements of the speckle pattern, leading to an estimate for the strain. Additionally, it is demonstrated that the optimal speckle size can be lower than the commonly reported optimum between two and five pixel pitches, necessary to circumvent aliasing in the image data. While this is shown for a measurement setup using 4f-optics, the results are of general importance to speckle-based strain or displacement measurement systems and should thus be taken into account.

FPGA-Microprocessor Based Sensor for Faults Detection in Induction Motors Using Time-Frequency and Machine Learning Methods.

Induction motors (IM) play a fundamental role in the industrial sector because they are robust, efficient, and low-cost machines. Changes in the environment, installation errors, or modifications to working conditions can generate faults in induction motors. The trend on IM fault detection is focused on the design techniques and sensors capable of evaluating multiple faults with various signals using non-invasive analysis. The methodology is based on processing electric current signals by applying the short-time Fourier transform (STFT). Additionally, the computation of the mean and standard deviation of infrared thermograms is proposed as main indicators. The proposed system combines both parameters by means of Support Vector Machine and k-nearest-neighbor classifiers. The development of the diagnostic system was done with digital hardware implementations using a Xilinx PYNQ Z2 card that integrates an FPGA with a microprocessor, thus taking advantage of the acquisition and processing of digital signals and images in hardware. The proposed method has proved to be effective for the classification of healthy (HLT), misalignment (MAMT), unbalance (UNB), damaged bearing (BDF), and broken rotor bar (BRB) faults with an accuracy close to 99%.

Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder

The Newcomb-Benford law, also known as Benford's law, is the law of anomalous numbers stating that in many real-life numerical datasets, including physical and statistical ones, numbers have a small initial digit. Numbers irregularity observed in nature leads to the question, is the arithmetical-logical unit, responsible for performing calculations in computers, optimal? Are there other architectures, not as regular as commonly used Parallel Prefix Adders, that can perform better, especially when operating on the datasets that are not purely random, but irregular? In this article, structures of a propagate-generate tree are compared including regular and irregular configurations—various structures are examined: regular, irregular, with gray cells only, with both gray and black, and with higher valency cells. Performance is evaluated in terms of energy consumption. The evaluation was performed using the extended power model of static CMOS gates. The model is based on changes of vectors, naturally taking into account spatio-temporal correlations. The energy parameters of the designed cells were calculated on the basis of electrical (Spice) simulation. Designs and simulations were done in the Cadence environment and calculations of the power dissipation were performed in MATLAB. The results clearly show that there are PPA structures that perform much better for a specific type of numerical data. Negligent design can lead to an increase greater than two times of power consumption. The novel architectures of PPA described in this work might find practical applications in specialized adders dealing with numerical datasets, such as, for example, sine functions commonly used in digital signal processing.

A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic

The purpose of the paper is to propose a new implementation of the PID (proportional–integral–derivative) algorithm in digital hardware. The proposed structure is optimized for cost. It follows a serialized, rather than parallel, scheme. It uses only one arithmetic block, performing the multiply-and-add operation. The calculations are carried out in a sequentially cyclic manner. The proposed circuit operates on standard single-precision (32-bit) floating-point numbers. It implements an extended PID formula, containing a non-ideal derivative component, and weighting coefficients, which enable reducing the influence of setpoint changes in the proportional and derivative components. The circuit was implemented in a Cyclone V FPGA (Field-Programmable Gate Array) device from Intel, Santa Clara, CA, USA. The proper operation of the circuit was verified in a simulation. For the specific implementation, which is reported in the paper, the sampling period of 516 ns was obtained, which means that the proposed solution is comparable in terms of speed with other hardware implementations of the PID algorithm operating on single-precision floating-point numbers. However, the presented solution is much more efficient in terms of cost. It uses 1173 LUT (Look-up Table) blocks, 1026 registers, and 1 DSP (Digital Signal Processing) block, i.e., about 30% of logic resources required by comparable solutions.

A Fast Factorized Back-Projection Algorithm Based on Range Block Division for Stripmap SAR

Fast factorized back-projection (FFBP) is a classical fast time-domain technique that has garnered significant success in spotlight synthetic aperture radar (SAR) signal processing. The algorithm’s efficiency has been extended to stripmap SAR through integral aperture determination and full-aperture data block processing while retaining its computational efficiency. However, the above method is only operated in the azimuth direction, and the computing efficiency needs to be urgently improved in the actual processing process. This paper proposes a fast factorized back-projection algorithm for stripmap SAR imaging based on range block division. The echo data are divided into multiple subblocks in the range direction, and FFBP processing is applied separately to each full-aperture subblock, further enhancing computational efficiency. The paper analyzes the algorithm’s principles, underscores the necessity of integral aperture determination and full-aperture data block processing, provides specific implementation steps, and applies the algorithm to point target simulation and experimental data from a vehicle-mounted ice radar. The experiments validate the algorithm’s efficiency in stripmap SAR imaging.

Discrete linear canonical shearlet transform

In this paper, we introduce the continuous and discrete version of the linear canonical shearlet transform (LCST). The authors begin with the definition of the LCST and then establish a relationship between the linear canonical transform (LCT) and the LCST. Next, the paper derives several basic properties like Parseval’s Formula, inversion formula, and the characterization of the transform’s range. In addition to the continuous version of the transform, the authors also present a discrete version of the LCST. This discrete version allows for practical implementation and efficient computation of the transform in digital signal processing systems. Lastly, the paper establishes a frame condition for the discrete LCST, which thereby helps in establishing the reconstruction formula for the discrete LCST. The paper ends with a conclusion.

Resource-aware Montgomery modular multiplication optimization for digital signal processing

Homomorphic encryption is an important technology for protecting data privacy, and the performance of modular multiplication directly affects the efficiency of homomorphic encryption. Currently, there are numerous FPGA-based acceleration techniques targeting modular multiplication. However, many of these implementations require substantial hardware resources or suffer from resource imbalance. This leads to a lower throughput. Therefore, we present a novel FPGA-based implementation of Montgomery Modular Multiplication aimed at addressing these challenges. Our design employs a suitable radix bit width and word size based on the digital signal processing (DSP) bit width rather than the conventional binary powers of two. We aim to instantiate more modular multipliers using limited resources while minimizing latency. We also introduce a novel DSP cascade structure, called parallel grouping cascade DSP, which reduces the number of clock cycles of internal multipliers. To balance the ratio of lookup table (LUT) and DSP usage, we also use multipliers implemented in the LUT to replace some DSPs. Our results, implemented on Xilinx Virtex-7 field-programmable gate array (FPGA), demonstrate more than 27% improvement in throughput on 1024-bit modular multiplication and more than 70% improvement on 2048-bit compared to the best previous state-of-the-art references.