Analog-to-digital Research Articles

Parallel photonic chip for nanosecond end-to-end image processing, transmission, and reconstruction

Image processing, transmission, and reconstruction constitute a major proportion of information technology. The rapid expansion of ubiquitous edge devices and data centers has led to substantial demands on the bandwidth and efficiency of image processing, transmission, and reconstruction. The frequent conversion of serial signals between the optical and electrical domains, coupled with the gradual saturation of electronic processors, has become the bottleneck of end-to-end machine vision. Here, we present an optical parallel computational array chip (OPCA chip) for end-to-end processing, transmission, and reconstruction of optical intensity images. By proposing constructive and destructive computing modes on the large-bandwidth resonant optical channels, a parallel computational model is constructed to implement end-to-end optical neural network computing. The OPCA chip features a measured response time of 6 ns and an optical bandwidth of at least 160 nm. Optical image processing can be efficiently executed with minimal energy consumption and latency, liberated from the need for frequent optical–electronic and analog–digital conversions. The proposed optical computational sensor opens the door to extremely high-speed processing, transmission, and reconstruction of visible contents with nanoseconds response time and terahertz bandwidth.

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

Predictors of young students’ school participation during the early days of COVID-19 remote learning

When the COVID-19 pandemic forced school closures in the U.S. in March 2020, children’s learning moved home and online, making school participation a challenge for many families, particularly those with low incomes. Although there is not a clear and agreed-upon digital analog for in-person school participation for young elementary students, existing research on young children’s school attendance and engagement in non-pandemic times suggests that family characteristics broadly recognized to shape child development (e.g., parental depressive symptoms, household chaos), children’s own characteristics (e.g., pre-COVID-19 academic skills, demographics), and logistical barriers with particular relevance to remote learning (e.g., internet access) may be determinants of remote learning participation. The current study explores the extent to which student participation during COVID-induced remote learning was predicted by family and child characteristics and logistical barriers by drawing on an existing study of diverse low-income students in Tulsa, OK who were in first grade when the pandemic emerged. We capitalize on unique, comprehensive, multi-informant data collected before and during COVID-19 to examine young children’s participation in remote learning while controlling for pre-existing differences that might otherwise be confounded with both COVID-related stressors and obstacles to remote learning participation. Both family characteristics (e.g., parent depression, household chaos, single mother) and logistical barriers (e.g., internet and device access) predicted children’s remote learning participation. Implications for school administrators and policymakers with a focus on preparation for future disasters that may once again force school closures − are discussed.

The influence of phase noise and nonlinear distortions of high-speed digital-to-analog converters on the parameters of digital communication systems

Problem statement. The trend in modern microwave electronics to transfer analog functions to the digital domain has led to the emergence and active use of high-speed digital-to-analog converters (DACs) in special operating modes in promising communication systems. However, optimization of power consumption and economic costs of signal generators (for example, through the use of simplified clock generators or by saving FPGA memory) leads to an increase in phase noise and nonlinear distortions in the output signal, which has a significant impact on the parameters of the communication system. Goal. Evaluation of phase noise and nonlinear distortions of signal generators based on high-speed digital-to-analog converters, as well as the study of their effect on the parameters of a digital communication system. Results. Expressions for estimating the spectral power density of phase noise of a signal generator based on a high-speed DAC are proposed. It is determined that the level of phase noise of the shaper is mainly determined by the noise of the clock generator. The jitter of the communication system was evaluated when using a surfactant generator and a PLL-based synthesizer as a clock generator. A mathematical model of the output signal of the shaper is proposed, taking into account nonlinear distortions caused by sampling, phase code truncation and amplitude quantization. A model of a communication system with multi-position quadrature amplitude modulation has been developed to evaluate parameters taking into account phase noise and nonlinear distortion of the shaper based on high-speed DACs. It is determined that the intrinsic phase noise of the signal generator leads to an increase in the probability of bit error (by about an order of magnitude compared to ideal formers). The use of surfactant generators as clock generators makes it possible to reduce the probability of bit errors of the communication system by 3-5 times compared with PLL-based synthesizers. Practical significance. It is shown that the displacement of points in the signal constellation is mainly influenced by nonlinear distortions of the output signal of high-speed DACs caused by truncation of the phase code, as well as incomplete suppression of spectral components located in the neighboring Nyquist zone. The proposed mathematical apparatus makes it possible to determine the optimal frequency ratios in the structure of the shaper, at which the lowest values of the displacement of the constellation points are achieved.

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit.

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of -0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

A hybrid SAR ADC with input range extension

—This paper proposes a differential 10-bit 1 MS/s successive approximation register (SAR) analog to digital converter (ADC) with input range (IR) extension. Employing 512 capacitor units and a reference voltage VREF, it attains a ±1.875VREF input range and a resolution of 10.91 bits. The hybrid SAR ADC decomposes the capacitive digital-to-analog converter (CDAC) into an incremental CDAC and a binary-weighted CDAC. For input signals larger than 0.75 VREF, the incremental CDAC is used to reduce the net sampling charge by biasing its capacitor bottom plates on proper reference voltage to implement input range extension. Furthermore, the increment CDAC contributes to enhancing linearity. The input frequency limitation is theoretically analyzed in the paper. This design is implemented with a 180-nm CMOS technology and achieves a 10.47 effective number of bits (ENOB). It consumes 26.8 μW at 1 MS/s with a 1.8-V supply and occupies an area of 0.0118 mm2.

Research on Clock Synchronization of Data Acquisition Based on NoC

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

A 36-nW Electrocardiogram Anomaly Detector Based on a 1.5-bit Non-Feedback Delta Quantizer for Always-on Cardiac Monitoring.

An always-on electrocardiogram (ECG) anomaly detector (EAD) with ultra-low power (ULP) consumption is proposed for continuous cardiac monitoring applications. The detector is featured with a 1.5-bit non-feedback delta quantizer (DQ) based feature extractor, followed by a multiplier-less convolutional neural network (CNN) engine, which eliminates the traditional high-resolution analog-to-digital converter (ADC) in conventional signal processing systems. The DQ uses a computing-in-capacitor (CIC) subtractor to quantize the sample-to-sample difference of ECG signal into 1.5-bit ternary codes, which is insensitive to low-frequency baseline wandering. The subsequent event-driven classifier is composed of a low-complexity coarse detector and a systolic-array-based CNN engine for ECG anomaly detection. The DQ and the digital CNN are fabricated in 65-nm and 180-nm CMOS technology, respectively, and the two chips are integrated on board through wire bonding. The measured detection accuracy is 90.6% ∼ 91.3% when tested on the MIT-BIH arrhythmia database, identifying three different ECG anomalies. Operating at 1 V and 1.4 V power supplies for the DQ and the digital CNN, respectively, the measured long-term average power consumption of the core circuits is 36 nW, which makes the detector among those state-of-the-art always-on cardiac anomaly detection devices with the lowest power consumption.

A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step.

EMG Instrumentation Modeling and Feature Processing Based On Discrete Wavelet Transform

Electromyography (EMG) instrumentation is essential in generating electrical signals from skeletal muscles. EMG sensors are helpful in various cases requiring the detection of human muscle contractions, neuromuscular disorders, and rehabilitation. EMG instrumentation is divided into two parts, namely, the analogue part and the digital part. The EMG instrumentation design comprises a digital-to-analog converter (DAC), instrumentation amplifier, filter, and analog-to-digital converter (ADC). Meanwhile, in digital signal processing adopting the Discrete Wavelet Transform (DWT) method, frequency analysis using DWT has proven superior. It is used in various research and has exceptionally detailed coefficient features for classifying neuromuscular disease signals. Therefore, this research aims to design analogue and digital EMG instrumentation and identify features in the form of detailed coefficients. The data used are two Physionet signals from the anterior tibialis body with myopathy and neuropathy disorders. The results obtained for EMG analogue instrumentation provide the expected results until they reach the filter component stage. The resulting signal forms a block in the filter component, different from the initial EMG signal. Meanwhile, the DWT decomposition results are of the Daubechies4 wavelet type with the highest level 17, which has a high detail coefficient at low frequencies, high dilation and the result of a mixture of neuropathy and myopathy EMG signals, or in other words, at low energies, this result is by the DWT theorem. Determining the efficiency of the DWT detailed coefficient feature requires further study with the same signal subject. The DWT features obtained can then be developed for various needs in EMG signal recognition.

Revolutionizing connectivity: Unleashing the power of 5G wireless networks enhanced by artificial intelligence for a smarter future

In the context of 5G wireless networks, this paper addresses a crucial concern—data loss in Analog-to-Digital Converters (ADCs) embedded within Multiple Input Multiple Output (MIMO) channels, a prevalent challenge in modern wireless communication systems. Despite the integration of ADCs in MIMO configurations to mitigate this issue, their implementation introduces significant complexities. In response to this, the paper introduces an innovative and efficient approach aimed at enhancing channel estimation in 5G MIMO systems. The proposed methodology relies on a heuristic-based optimization technique within a channel prediction framework. The framework uses feedback information collected through a Cascade Fusion Serial Network (CFSN) to analyze the receiver-side error ratio and estimate the channel coefficients of MIMO systems at the transmitter. An attention mechanism is incorporated into the model design through the use of a Convolutional Neural Networks - Gated Recurrent Units (CNN-GRU) and a Multi-Scaled Stacked Auto encoder. Parameters of Attention CNN-GRU, Stacked Auto encoder, and CFSN are refined using the Whale Optimization method. The optimization objective is to minimize key metrics, including Root Mean Squared Error (RMSE), Bit Error Rate (BER), and Mean Squared Error (MSE) associated with the estimated channel. Experimental evaluations underscore the efficacy of the proposed MIMO model in the context of 5G networks. The results demonstrate improved convergence rates, heightened prediction performance, and reduced computational costs compared to existing methods. This research contributes valuable insights into addressing data loss challenges specific to 5G MIMO systems, providing a pioneering solution that integrates heuristic optimization, advanced neural network architectures, and nature-inspired algorithms for parameter tuning.

Design and Implementation of a Cost‐Effective, Portable Impedance Analyzer Device with AD5941

This study proposes a cost‐effective, small‐size, and portable impedance analyzer using the AD5941 Analog Front End (AFE) that makes frequency sweep measurement for various applications. The design utilizes a microcontroller and an AD5941 circuit for impedance measurement. The AD541 is a high precision impedance converter system that consists of a 16‐bit, 1.6 MSPS, analog to digital converter (ADC), an integrated waveform generator, and a digital signal processing (DSP) block. The AD5941 has many advantages over the AD5933 which was used in numerous studies in the past decade. Also, the device implements the four‐wire impedance method which is an impedance measuring technique that reduces the effect of electrodes to achieve higher accuracy. A supporting Graphic User Interface (GUI) software is employed to control the Impedance Analyzer device and to visualize the measurement. This impedance analyzer achieves a frequency resolution of 0.015 Hz and can generate sinusoid up to 200 kHz. In frequency range from 10 kHz to 150 kHz, the device can measure impedance in the range of 10 Ω–100 kΩ with less than 4.3% of error in comparison with benchtop impedance analyzer, Microtest 6632. Moreover, our impedance measurement device has undergone testing involving human calf measurements and electrochemical quantification, particularly for estimating Sodium Chlorite. The experimental outcomes demonstrate that our design not only fulfills the criteria of an impedance analyzer device but also performs effectively across diverse applications. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Remaining useful life prediction for stochastic degrading devices incorporating quantization

Quantization has been widely employed in analog-to-digital conversion (ADC) for the acquisition of digital data, which are further utilized for prognostics. However, quantization errors are inevitable during ADC, resulting in bias in the subsequent prognosis results. Compared to the numerous researches on prognosis considering measurement noises, slight attention has been paid on remaining useful life (RUL) for degrading devices incorporating quantization errors. In this study, a Wiener-process-based model incorporating mixed random noise is utilized to describe the degradation process involving quantization errors. In order to mitigate the impact of quantization errors, a parameter identification approach and a degradation state estimation method are proposed, which integrate maximum likelihood estimation, particle filter, and Bayesian inference. Subsequently, the results of RUL prediction with and without considering quantization errors are derived, respectively. Finally, numerical examples and a case study of the control moment gyroscopes (CMG) and batteries are provided to demonstrate the proposed method.

ОСОБЛИВОСТІ ПОБУДОВИ ІМПЕДАНСОМЕТРИЧНИХ КАНАЛІВ ДЛЯ РОБОТИ НА НИЗЬКИХ ТА ІНФРАНИЗЬКИХ ЧАСТОТАХ

The features of the low and infra-low frequency ranges of harmonic measurement signals, as well as the properties of the investigated objects, which must be taken into account during the construction of impedance measuring channels, are determined. To combine the necessary metrological characteristics of such channels (accuracy, speed, immunity), an approach is used, consisting in analog-to-digital conversion of signals received from sensors, and subsequent application of digital methods of their processing. Options for implementing this approach using digital methods for determining the amplitude of sinusoidal signals were considered and analyzed, among which the most promising ones were selected for metrological support of impedance measurements at low and infra-low frequencies. The perspective of using parallel-serial analog-digital conversion of an informative signal with its continuous integration at these frequencies is shown. Conclusions were made and recommendations were given regarding the use of the considered methods taking into account the properties of the measurement objects. References 16.

Electrode module for EIT with a robust howland current source

Electrical Impedance Tomography (EIT) is a non-invasive imaging technique that reconstructs internal conductivity distributions of a body from electrical measurements taken on its boundary. This study contributes to the field by focusing on the technological intricacies of absolute EIT imaging, which is challenged by limitations such as the resolution capacity of the hardware and the complexities introduced by imaging capacitive bodies. The novel EIT system architecture proposed enhances the accuracy of measurement by integrating current sources and Analog-to-Digital Converters (ADCs) closer to the electrodes, employing alternating current excitations to accurately capture phase information. This system uses a dynamic arrangement of surface electrodes that continuously alter their roles between current injection and voltage measurement, in a synchronized sequence, to ensure the accuracy of the measurements. The paper describes the design and implementation of both the excitation and measurement subsystems, highlighting the use of digital signal demodulation near the electrode to reduce data transfer issues. Experimental results confirm the system’s capability for real-time image reconstruction at 50 frames per second with precision in phase delay measurements, suggesting significant potential for clinical and industrial applications. Future work will aim to further refine signal generation with higher-speed DACs and expand to image reconstruction with more channels.

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

Real-time generation of circular patterns in electron beam lithography

Electron beam lithography (EBL) involves the transfer of a pattern onto the surface of a substrate by first scanning a thin layer of organic film (called resist) on the surface by a tightly focused and precisely controlled electron beam (exposure) and then selectively removing the exposed or nonexposed regions of the resist in a solvent (developing). It is widely used for fabrication of integrated circuits, mask manufacturing, photoelectric device processing, and other fields. The key to drawing circular patterns by EBL is the graphics production and control. In an EBL system, an embedded processor calculates and generates the trajectory coordinates for movement of the electron beam, and outputs the corresponding voltage signal through a digital-to-analog converter (DAC) to control a deflector that changes the position of the electron beam. Through this procedure, it is possible to guarantee the accuracy and real-time control of electron beam scanning deflection. Existing EBL systems mostly use the method of polygonal approximation to expose circles. A circle is divided into several polygons, and the smaller the segmentation, the higher is the precision of the splicing circle. However, owing to the need to generate and scan each polygon separately, an increase in the number of segments will lead to a decrease in the overall lithography speed. In this paper, based on Bresenham’s circle algorithm and exploiting the capabilities of a field-programmable gate array and DAC, an improved real-time circle-producing algorithm is designed for EBL. The algorithm can directly generate circular graphics coordinates such as those for a single circle, solid circle, solid ring, or concentric ring, and is able to effectively realizes deflection and scanning of the electron beam for circular graphics lithography. Compared with the polygonal approximation method, the improved algorithm exhibits improved precision and speed. At the same time, the point generation strategy is optimized to solve the blank pixel and pseudo-pixel problems that arise with Bresenham’s circle algorithm. A complete electron beam deflection system is established to carry out lithography experiments, the results of which show that the error between the exposure results and the preset patterns is at the nanometer level, indicating that the improved algorithm meets the requirements for real-time control and high precision of EBL.

Study on low power ADC Design using Memristor on Embedded systems

As portable and battery-operated devices become more common, embedded systems must meet the highest standards for low power consumption. Conventional analog-to-digital converters (ADCs) add a substantial amount of power to these systems overall. The design and application of low power ADCs using memristor technology are examined in this work. Memristors present a viable substitute for traditional ADC components because of their high density and non-volatile memory capabilities. Through the utilization of memristors' special qualities—like their low voltage operation and powerlessness—this research attempts to create ADC architectures with much lower power consumption. The suggested design creates a small, effective, and power-saving solution by integrating memristors in the analog front end and digital processing stages of the ADC. According to experimental results, memristor-based ADCs can save a significant amount of power without sacrificing performance, which makes them perfect for next-generation embedded systems applications. By advancing the design of energy-efficient embedded systems, this study may prolong the lifespan of portable electronics and open up new applications in wearable and Internet of Things (IOT) technologies.