Digital-to-analog Converter Circuit Research Articles

Design principles of digital-to-analog conversion in information transformation

The object of study is digital-to-analog converter (DAC). The meaning of DAC, their design and control of various types of switches, as well as some logic elements that can act as a switch, as well as the principles of DAC operation based on various series, microcircuits were considered. The resistance of a 4-bit DAC circuit was calculated and, accordingly, the change in the output voltage when applying the corresponding combined input voltage was studied, and a timing diagram was accordingly developed. Using 1-state and toggle physical switches, schematics are established and side effects are learned. Ladder circuit established using R–2R type dividers as voltage dividers. The object of the research is to find and learn the most technologically advantageous concept in order to provide good communication between all equipments by transferring information from digital to analog in the industrial field as well as in other areas where automation is used. One of the biggest challenges in this research is to determine the smallest binary values. Before the use of electronic logic elements such as counters, bistable physical switches were used to create a break or connect state in the circuit, which caused additional energy and time loss or abrasion because of large voltages occur across the switches. The biggest issue was that when manufacturing integrated digital-to-analog converters, producing the right resistors with very different values is really difficult. As a result of this research, it is seen that the use of physical switches is unnecessary as a demand of today's modern technology, and integrated microcircuits are good to replace them. The programming of digital-to-analog converters on programmable hardware devices such as Arduino and Raspberry Pi were mentioned. If to predict the near future, digital-to-analog transmission will be realized only by only using logic elements, and this will change both their energy efficiency and size for the better.

ECG Simulator Based on Microcontroller Equipped with Arrhythmia Signal

Electrocardiograph (ECG) is one of the diagnostic sciences that is often studied in modern medicine, used to detect damage to the components of the heart or disorders of the heart rhythm called arrhythmias. The purpose of this research is to develop an Electrocardiograph simulator that is equipped with arrhythmia. The main design consists of an Arduino Mega 2560 microcontroller, MCP4921 DAC (Digital to Analog Converter) circuit, a network resistor, and a sensitivity selection circuit. The MCP4921 type DAC converts the digital signal data into analog data which will then be forwarded to the resistor network circuit as a signal formation for each lead. The basic signal image data used for the formation of normal Electrocardiograph and arrhythmias were taken from the Electrocardiograph recorder using Phantom Electrocardiograph. Based on the readings on the Beat Per Minute setting of the module to the Beat Per Minute printout on the Electrocardiograph recorder, the error rate value for the Normal Sine Rhythm parameter is 0.790% for Beat Per Minute 30, 0.383% for Beat Per Minute 60, 0.535% for Beat Per Minute 120, 0.515% for Beat Per Minute 180 and 0.593% for Beat Per Minute 240. The error rate for the Arrhythmia parameter is 2.076% for ventricular tachycardia Beat Per Minute 160 and 0.494% for Supraventricular Tachycardia Beat Per Minute 200. The design of the Electrocardiograph simulator can simulate the signals of the human body and it can be used as a medium in the learning process in the world of health

A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

A 4-bit, third-order, continuous-time $\Sigma \Delta$ modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance $\Sigma \Delta$ modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm2.

Distribution characteristic of p-channel metal-oxide-semiconductor negative bias temperature instability effect under process variations

Negative bias temperature instability (NBTI) is a p-channel metal-oxide-semiconductor (PMOS) degradation mechanism, which becomes one of the important reliability concerns. The NBTI drastically influences device performance and circuit lifetime. On the other hand, the circuit performance is also affected by the fabrication-induced process variation when the transistor size shrinks to a nanometer-scale. In the presence of the fabrication-induced random variations, the NBTI aging process and its influence on PMOS device become a random process. In this paper, the joint effects of NBTI and process variations on PMOS device are investigated. Firstly, the influence of process variation on NBTI aging is analyzed based on the reaction-diffusion (R-D) mechanism. The NBTI-induced PMOS threshold voltage degradation depends not only on stress time but also on fabrication-determined process parameters, such as the initial threshold voltage and oxide thickness. Then the statistical model is proposed to model NBTI-induced aging under process variation, which captures the threshold voltage variation and oxide thickness variation as random vectors with normal distributions. For 100-times Monte-Carlo simulation based on 65 nm technology, the voltage error and oxide thickness error of the PMOS device are obtained. Applying these process errors to the statistical model, the results show that mean value of threshold voltages is increased along the negative direction with the stress time going on under the process variation and NBTI effect interaction. Meanwhile the standard deviation of threshold voltage is reduced, which represents that the matching between those PMOS devices becomes better. The proposed statistical model accuracy is verified by R-D model theoretical solutions. The maximum relative error of the mean value and of the standard deviations for the threshold voltages degradation of the PMOS device are only 0.058% and 0.91% respectively in 104 s. The distribution characteristic of PMOS NBTI effect is more serious to analog circuit, because analog circuit is more sensitive to device mismatch. For current steering digital-to-analog converter (DAC), PMOS device is always adopted as current source due to its good isolating properties. The PMOS current source requires good matching, and mismatch error could cause circuit failure. To realize aging simulation on DAC circuit in Spectre environment, the above statistical NBTI model is realized by Verilog-ASM language as the subcircuit module to PMOS device. Finally, this module is applied to the current steering DAC. Considering the NBTI effect under process variations, the simulation results show that the DAC gain error is increased with the stress time going on, while its linearity error is gradually reduced.

A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit

In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter

A circuit topology suitable for the implementation of operational amplifiers (OPAMPs) in an amorphous-silicon (a-Si) thin-film-transistor (TFT) technology is presented in this paper. Due to the use of a positive feedback in the input differential pair, the gain of the OPAMP is effectively boosted, facilitating analog circuit designs for system-on-panel (SoP) applications. Based on the proposed technique, a 4-bit digital-to-analog converter (DAC) prototype, which consists of a resistor string and a unity-gain buffer, is developed. The DAC is implemented by using an 8-¿m a-Si NTFT process. Operated at a supply voltage of 25 V, the fabricated circuit consumes a dc power of 3.68 mW. For an output voltage range from 9.5 to 12.5 V, the measurement results indicate a differential non-linearity (DNL) of ±0.216 LSB and an integral non-linearity (INL) of ±0.667 LSB. With a settling time less than 1.1 ms, the DAC circuit can operate at a maximum conversion rate of 0.9 kS/s.

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Abstract— Low‐temperature polysilicon (LTPS) technology has a tendency towards integrating all circuits on glass substrate. However, the poly‐Si TFTs suffered poor uniformity with large variations in the device characteristics due to a narrow laser process window for producing large‐grained poly‐Si TFTs. The device variation is a serious problem for circuit realization on the LCD panel, so how to design reliable on‐panel circuits is a challenge for system‐on‐panel (SOP) applications. In this work, a 6‐bit R‐string digital‐to‐analog converter (DAC) with gamma correction on glass substrate for TFT‐panel applications is proposed. The proposed circuit, which is composed of a folded R‐string circuit, a segmented digital decoder, and reordering of the decoding circuit, has been designed and fabricated in a 3‐μm LTPS technology. The area of the new proposed DAC circuit is effectively reduced to about one‐sixth compared to that of the conventional circuit for the same LTPS process.

A First-Order Tree-Structured DAC With Reduced Signal-Band Noise

A mismatch-shaping tree-structured digital-to-analog converter (DAC) utilizes several layers of switching blocks to spectrally shape the DAC circuit errors. A first-order mismatch-shaping DAC using un-dithered switching sequences for the switching blocks results in spurious tones in the DAC noise. The unwanted tones can be eliminated from the DAC noise by employing white dither sequences to randomly select two types of short root symbols to be placed in the switching sequences. Dithered switching sequences, unfortunately, result in a higher noise floor in the DAC noise, in comparison with un-dithered switching sequences. In this brief, we propose an improved first-order sequencing logic to eliminate unwanted tones while causing only a modest increase in the in-band noise floor at a very modest hardware cost. Our mismatch-shaping sequencing logic is based on the scheme using a white dither sequence to randomly select each symbol between two specific types of long root symbols. Alternatively, our scheme can be viewed as using a high-pass dither sequence to randomly select the short root symbols. An analytical formula for the power-spectral density of the proposed switching sequence is presented to show its improvement over the prior first-order switching sequence. It is also shown from numerical simulations that the proposed switching sequence improves the signal-to-noise plus distortion ratio by more than 5 dB for a sigma-delta modulator with static DAC-element errors chosen from a Gaussian distribution with a standard deviation of 1%

Hybrid 8-bit Digital-to-Analog Converter for Mobile Active Matrix Flat Panel Displays Using Low-Temperature Polycrystalline Silicon Thin Film Transistors

To implement a compact-area 8-bit digital-to-analog converter (DAC) for system-on-panel (SoP) application, a panel DAC concept is proposed to apply a cyclic DAC to low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) driver circuits, which utilizes a pair of data lines as capacitors for the cyclic DAC. This means that a large part of the DAC circuit is implemented on the pixel area, thus saving the peripheral circuit area for the DAC. Another important impact of the proposed scheme is that we can eliminate the buffer amplifier to drive the capacitive data lines, because the analog voltage of the DAC is produced on the data line itself. However, the capacitances of two data lines should match with a 1% difference for the 8-bit cyclic DAC. The data line capacitance is basically parasitic and is fabricated by wet etching, so such tight matching is almost impossible. Therefore, the use of the hybrid DAC which combines a 6-bit resistor-string DAC and a 2-bit cyclic DAC is a more feasible approach, because the capacitance difference of up to 50% between the two data lines is allowed for the 2-bit cyclic DAC. The area increase in the 8-bit hybrid DAC is limited to 21% compared with that in the 6-bit resistor-string DAC, and the power consumption is about 13.3 mW for a 2-in. quarter video graphic array (qVGA) active matrix organic light emitting diode (AMOLED) panel.

Method and system for reducing pop noise of a sound broadcasting instrument

A method and system are disclosed for controlling pop noises in a sound broadcasting system. After controllably connecting an output of a drive amplifier to a first predetermined low voltage level through a first switch, a first portion of an operation control data set is input to a digital-to-analog converter (DAC) circuit for driving an output thereof to a second predetermined low voltage level, and a second portion of the operation control data set is also input to the DAC circuit and further to the drive amplifier to bring the output of the drive amplifier to a common mode voltage level over a predetermined rise-up time period for controlling the pop noises.

Use of electron cyclotron resonance x-ray source for nondestructive testing application

Electron cyclotron resonance (ECR) technique is being used for generating x rays in the low-energy region (<150keV). Recently, the source is used for the calibration of thermoluminescent dosimetry (TLD) badges. In order to qualify the ECR x-ray source for imaging application, the source should give uniform flux over the area under study. Lead collimation arrangement is made to get uniform flux. The flux profile is measured using a teletector at different distance from the port and uniform field region of 10×10cm2 has been marked at 20cm from the x-ray exit port. A digital-to-analog converter (DAC) circuit pack is used for examining the source performance. The required dose for nondestructive testing examination has been estimated using a hospital x-ray machine and it is found to be 0.05mSv. Our source experimental parameters are tuned and the DAC circuit pack was exposed for nearly 7min to get the required dose value. The ECR x-ray source operating parameters are argon pressure: 10−5Torr, microwave power: 350W, and coil current: 0A. The effective energy of the x-ray spectrum is nearly 40keV. The x-ray images obtained from ECR x-ray source and hospital medical radiography machine are compared. It is found that the image obtained from ECR x-ray source is suitable for NDT application.