Analog-to-digital Converter Architecture Research Articles

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

Study on low power ADC Design using Memristor on Embedded systems

As portable and battery-operated devices become more common, embedded systems must meet the highest standards for low power consumption. Conventional analog-to-digital converters (ADCs) add a substantial amount of power to these systems overall. The design and application of low power ADCs using memristor technology are examined in this work. Memristors present a viable substitute for traditional ADC components because of their high density and non-volatile memory capabilities. Through the utilization of memristors' special qualities—like their low voltage operation and powerlessness—this research attempts to create ADC architectures with much lower power consumption. The suggested design creates a small, effective, and power-saving solution by integrating memristors in the analog front end and digital processing stages of the ADC. According to experimental results, memristor-based ADCs can save a significant amount of power without sacrificing performance, which makes them perfect for next-generation embedded systems applications. By advancing the design of energy-efficient embedded systems, this study may prolong the lifespan of portable electronics and open up new applications in wearable and Internet of Things (IOT) technologies.

An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators

Mismatch of the digital-to-analog converter (DAC) elements is the major limitation for Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in multi-bit Delta Sigma Modulators (DSM). In this article we extend a previously introduced technique to build an intrinsically linear 13 level DAC. An exemplary Switched-Capacitor (SC) 13-levels 20 kHz discrete-time DSM employing this technique is simulated and achieves an SFDR higher than 100 dBc on circuit level in presence of considerable capacitor mismatch. The presented DAC architecture is not limited to be used in a discrete-time modulator, but could also be employed in a Continuous-Time DSM (CTDSM).

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled Gm-C Integrator

This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13.5~\mu \text{W}$ </tex-math></inline-formula> , leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.

Design of 8-Bit Hybrid Current Steering Digital to Analog Converter in a Standard 65nm CMOS Technology

A digital-to-analog converter (DAC) in electronics is a device that transforms digital signals into analog signals. There are various DAC architectures, and DAC's usefulness for a given application is determined by factors like resolution, INL, DNL, power consumption, maximum sampling frequency, and others. Because digital-to-analog conversion may damage a signal, a DAC with negligible faults for the application should be used. The current-steered digital-to-analog converter is well suited for high-speed applications because no buffers are needed for current steering architectures and the output is the total current drawn from the supply. In this paper, an 8-bit hybrid current steering digital-to-analog converter is proposed. Four cascode current sources with different weights are used in this architecture. The UMC 65nm CMOS technology was used to design the digital-to-analog converter. The INL and DNL were +0.19/-0.15 LSB and +0.28/-0.11 LSB respectively. The DAC uses roughly 3.25 mW at a supply voltage of 1.2V and a sample rate of 100 MHz. 12.751 mV was the output voltage at full scale. In comparison to earlier reports, the power, INL, DNL, and chip area used by the digital-to-analog converter in this architecture were significantly lower. It is appropriate for use in portable devices.

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

Pipelined Memristive Analog-to-Digital Converter With Self-Adaptive Weight Tuning

Benefiting from area and power efficiency, memristors enable the development of neural network analog-to-digital converter (ADC) to break through the limitations of conventional ADCs. Although some memristive ADC (mADC) architectures have been proposed recently, the current research is still at an early stage, which is mainly on the simulation and requires numerous target labels to train the synapse weights. In this paper, we propose a pipelined Hopfield neural network mADC architecture and experimentally demonstrate that such mADC has the capability of self-adaptive weight tuning. The proposed training algorithm is an unsupervised method originated from the random weight change (RWC) algorithm, which is modified to reduce the complexity of error feedback circuit to make it more hardware friendly. The synapse matrix could be adapted to the 1T1R crossbar array. For an 8-bit two-stage pipelined mADC, the proposed architecture in the simulation could achieve 7.69 fJ/conv FOM, 7.90 ENOB, 0.1 LSB INL, and 0.1 LSB DNL. And the experimental performance only achieves 1.56 pJ/conv FOM, 7.59 ENOB, 0.21 LSB INL, and 0.29 LSB DNL, which is mainly limited by the comparator’s switching time.

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR &amp; VCO ADC

We present an OTA-free 1–1 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage-controlled oscillator (VCO) as the second stage. The key contribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuation due to passive charge sharing in the NS-SAR to linearize the VCO. The MASH architecture suppresses quantization noise and SAR comparator noise at the ADC output, and the high pass shapes VCO thermal noise. In addition, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16 mW while achieving an SNDR/DR of 71.5/75.8 dB over a 1.1-MHz bandwidth and Walden FoM of 23.3 fJ/step, which is the lowest in 65-nm technology.

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications.

Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm2 Switched-Capacitor DAC in 16-nm FinFET CMOS

This article presents a compact 2× time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC's architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 16-nm CMOS and supports up to 0.32- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> signal swing across its differential 100- Ω load. It achieves an SFDR ≥ 37 dB and an IM 3 ≤ -45.6 dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply.

Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications

Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for complex, flexible, and robust signal processing algorithms in the digital domain, as well as easy implementation of advanced modulation schemes beyond binary PAM2. However, the power consumption of the ADC and ensuing digital equalization is a key issue for such receivers in high-speed applications. Embedding analog equalization inside the ADC architecture allows for both a lower ADC resolution and a reduced-complexity digital equalizer, resulting in a more power-efficient receiver. This article presents a 6-bit 1.5-GS/s time-interleaved successive approximation register (SAR) ADC with low-overhead two-tap embedded decision-feedback equalizer (DFE). A smart speculative DFE is proposed to reduce additional conversion cycles required for the equalization realization in the ADC. Moreover, DFE functions are efficiently embedded in the capacitive digital-to-analog converter (DAC) references. The prototype ADC with two-tap DFE is implemented in a 130-nm CMOS process and achieves a 5.24-bit peak effective number of bits and 0.59-pJ/conversion-step figure-of-merit (FOM) at a 1.5-GS/s sampling rate while consuming 34.1 mW and occupying a core area of 0.32 mm2. The effectiveness of the embedded DFE in timing margin improvement is verified for 1.5-Gb/s operation over high-loss FR4 channels at a bit error rate (BER) of 10−9.

A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).

A Scalable Discrete-Time Integrated CMOS Readout Array for Nanopore Based DNA Sequencing

This paper introduces a high-speed mixed-signal readout array in 130-nm CMOS for the amplification and digitization of picoampere-range signals. Its design is inspired by the needs of emerging DNA sequencing technologies based on biological nanopore sensors. To overcome switching and substrate noise this system adopts an in-pixel analog-to-digital converter (ADC) architecture and a novel readout technique while consuming 10x less power than similar designs described in the literature. The in-pixel ADC architecture is inherently scalable and immune to electrical interference which can be extended to 100s of channels. With a 5 pF input capacitance, the amplifiers achieve a maximum bandwidth of 100 kHz and demonstrate a noise floor as low as 4 fA/ $\sqrt {\text{Hz}}$ and a gain in the range of $\text{G}\Omega $ at 10 kHz. Circuit noise behaviour and theoretical maximum performance estimates using behavioural models are also discussed.

Single-Slope Look-Ahead Ramp ADC for CMOS Image Sensors

Integrating type analog-to-digital converters (ADC) used in column-parallel CMOS image sensors trade conversion speed with size, power, and complexity to achieve optimal performance. A new integrating ADC architecture called single-slope look-ahead ramp (SSLAR) ADC is introduced in this paper. It utilizes a statistical approach and code-prediction methods to improve the conversion speed of standard single-slope ramp (SSR) ADC. It is shown that SSLAR ADC reduces power consumption while achieving an increased frame rate. This is achieved by the SSLAR algorithm that was optimized for column-parallel CMOS active pixel sensor (APS) imager architecture. A 10-bit SSLAR ADC was designed in a 0.5μm CMOS (2P3M) process and integrated with a column-parallel CMOS image sensor that has 200 × 150 array with 15μm pixels. Measurements showed that a 6× frame rate increase can be achieved while reducing power consumption 13% with minimal impact on image quality.

Four innovative calibration algorithms for capacitive mismatch in 18‐bit redundant split SAR ADC

SummaryFour calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog‐to‐digital converter (ADC). An 18‐bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte‐Carlo runs with a standard deviation of 0.1% (σ0/C0 = 0.001). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64‐dB enhancement of spurious‐free dynamic range (SFDR) and a 3.33‐bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re‐exchanging method I (SREI) show that a 21.64‐dB enhancement of SFDR and a 3.34‐bit improvement of ENOB have achieved, respectively

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.

An opamp-free second-order noise-shaping SAR ADC with 4$$\times$$ passive gain using capacitive charge pump

This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration on filter capacitors are obviated. It implements 4 $$\times$$ passive gain by capacitive charge-pump techniques that compensates the partial loss of residue voltage and relaxes the specifications of comparator. According to the behavioral modeling and simulation results, an ENOB of 16.88-bit is achieved based on a 10-bit DAC array, at the OSR of 16. Through utilizing the Monte Carlo simulation, the proposed ADC architecture is proven to be a robust system.