Analog-to-digital Research Articles

A 36-nW Electrocardiogram Anomaly Detector Based on a 1.5-bit Non-Feedback Delta Quantizer for Always-on Cardiac Monitoring.

An always-on electrocardiogram (ECG) anomaly detector (EAD) with ultra-low power (ULP) consumption is proposed for continuous cardiac monitoring applications. The detector is featured with a 1.5-bit non-feedback delta quantizer (DQ) based feature extractor, followed by a multiplier-less convolutional neural network (CNN) engine, which eliminates the traditional high-resolution analog-to-digital converter (ADC) in conventional signal processing systems. The DQ uses a computing-in-capacitor (CIC) subtractor to quantize the sample-to-sample difference of ECG signal into 1.5-bit ternary codes, which is insensitive to low-frequency baseline wandering. The subsequent event-driven classifier is composed of a low-complexity coarse detector and a systolic-array-based CNN engine for ECG anomaly detection. The DQ and the digital CNN are fabricated in 65-nm and 180-nm CMOS technology, respectively, and the two chips are integrated on board through wire bonding. The measured detection accuracy is 90.6% ∼ 91.3% when tested on the MIT-BIH arrhythmia database, identifying three different ECG anomalies. Operating at 1 V and 1.4 V power supplies for the DQ and the digital CNN, respectively, the measured long-term average power consumption of the core circuits is 36 nW, which makes the detector among those state-of-the-art always-on cardiac anomaly detection devices with the lowest power consumption.

A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step.

EMG Instrumentation Modeling and Feature Processing Based On Discrete Wavelet Transform

Electromyography (EMG) instrumentation is essential in generating electrical signals from skeletal muscles. EMG sensors are helpful in various cases requiring the detection of human muscle contractions, neuromuscular disorders, and rehabilitation. EMG instrumentation is divided into two parts, namely, the analogue part and the digital part. The EMG instrumentation design comprises a digital-to-analog converter (DAC), instrumentation amplifier, filter, and analog-to-digital converter (ADC). Meanwhile, in digital signal processing adopting the Discrete Wavelet Transform (DWT) method, frequency analysis using DWT has proven superior. It is used in various research and has exceptionally detailed coefficient features for classifying neuromuscular disease signals. Therefore, this research aims to design analogue and digital EMG instrumentation and identify features in the form of detailed coefficients. The data used are two Physionet signals from the anterior tibialis body with myopathy and neuropathy disorders. The results obtained for EMG analogue instrumentation provide the expected results until they reach the filter component stage. The resulting signal forms a block in the filter component, different from the initial EMG signal. Meanwhile, the DWT decomposition results are of the Daubechies4 wavelet type with the highest level 17, which has a high detail coefficient at low frequencies, high dilation and the result of a mixture of neuropathy and myopathy EMG signals, or in other words, at low energies, this result is by the DWT theorem. Determining the efficiency of the DWT detailed coefficient feature requires further study with the same signal subject. The DWT features obtained can then be developed for various needs in EMG signal recognition.

Revolutionizing connectivity: Unleashing the power of 5G wireless networks enhanced by artificial intelligence for a smarter future

In the context of 5G wireless networks, this paper addresses a crucial concern—data loss in Analog-to-Digital Converters (ADCs) embedded within Multiple Input Multiple Output (MIMO) channels, a prevalent challenge in modern wireless communication systems. Despite the integration of ADCs in MIMO configurations to mitigate this issue, their implementation introduces significant complexities. In response to this, the paper introduces an innovative and efficient approach aimed at enhancing channel estimation in 5G MIMO systems. The proposed methodology relies on a heuristic-based optimization technique within a channel prediction framework. The framework uses feedback information collected through a Cascade Fusion Serial Network (CFSN) to analyze the receiver-side error ratio and estimate the channel coefficients of MIMO systems at the transmitter. An attention mechanism is incorporated into the model design through the use of a Convolutional Neural Networks - Gated Recurrent Units (CNN-GRU) and a Multi-Scaled Stacked Auto encoder. Parameters of Attention CNN-GRU, Stacked Auto encoder, and CFSN are refined using the Whale Optimization method. The optimization objective is to minimize key metrics, including Root Mean Squared Error (RMSE), Bit Error Rate (BER), and Mean Squared Error (MSE) associated with the estimated channel. Experimental evaluations underscore the efficacy of the proposed MIMO model in the context of 5G networks. The results demonstrate improved convergence rates, heightened prediction performance, and reduced computational costs compared to existing methods. This research contributes valuable insights into addressing data loss challenges specific to 5G MIMO systems, providing a pioneering solution that integrates heuristic optimization, advanced neural network architectures, and nature-inspired algorithms for parameter tuning.

Design and Implementation of a Cost‐Effective, Portable Impedance Analyzer Device with AD5941

This study proposes a cost‐effective, small‐size, and portable impedance analyzer using the AD5941 Analog Front End (AFE) that makes frequency sweep measurement for various applications. The design utilizes a microcontroller and an AD5941 circuit for impedance measurement. The AD541 is a high precision impedance converter system that consists of a 16‐bit, 1.6 MSPS, analog to digital converter (ADC), an integrated waveform generator, and a digital signal processing (DSP) block. The AD5941 has many advantages over the AD5933 which was used in numerous studies in the past decade. Also, the device implements the four‐wire impedance method which is an impedance measuring technique that reduces the effect of electrodes to achieve higher accuracy. A supporting Graphic User Interface (GUI) software is employed to control the Impedance Analyzer device and to visualize the measurement. This impedance analyzer achieves a frequency resolution of 0.015 Hz and can generate sinusoid up to 200 kHz. In frequency range from 10 kHz to 150 kHz, the device can measure impedance in the range of 10 Ω–100 kΩ with less than 4.3% of error in comparison with benchtop impedance analyzer, Microtest 6632. Moreover, our impedance measurement device has undergone testing involving human calf measurements and electrochemical quantification, particularly for estimating Sodium Chlorite. The experimental outcomes demonstrate that our design not only fulfills the criteria of an impedance analyzer device but also performs effectively across diverse applications. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Remaining useful life prediction for stochastic degrading devices incorporating quantization

Quantization has been widely employed in analog-to-digital conversion (ADC) for the acquisition of digital data, which are further utilized for prognostics. However, quantization errors are inevitable during ADC, resulting in bias in the subsequent prognosis results. Compared to the numerous researches on prognosis considering measurement noises, slight attention has been paid on remaining useful life (RUL) for degrading devices incorporating quantization errors. In this study, a Wiener-process-based model incorporating mixed random noise is utilized to describe the degradation process involving quantization errors. In order to mitigate the impact of quantization errors, a parameter identification approach and a degradation state estimation method are proposed, which integrate maximum likelihood estimation, particle filter, and Bayesian inference. Subsequently, the results of RUL prediction with and without considering quantization errors are derived, respectively. Finally, numerical examples and a case study of the control moment gyroscopes (CMG) and batteries are provided to demonstrate the proposed method.

ОСОБЛИВОСТІ ПОБУДОВИ ІМПЕДАНСОМЕТРИЧНИХ КАНАЛІВ ДЛЯ РОБОТИ НА НИЗЬКИХ ТА ІНФРАНИЗЬКИХ ЧАСТОТАХ

The features of the low and infra-low frequency ranges of harmonic measurement signals, as well as the properties of the investigated objects, which must be taken into account during the construction of impedance measuring channels, are determined. To combine the necessary metrological characteristics of such channels (accuracy, speed, immunity), an approach is used, consisting in analog-to-digital conversion of signals received from sensors, and subsequent application of digital methods of their processing. Options for implementing this approach using digital methods for determining the amplitude of sinusoidal signals were considered and analyzed, among which the most promising ones were selected for metrological support of impedance measurements at low and infra-low frequencies. The perspective of using parallel-serial analog-digital conversion of an informative signal with its continuous integration at these frequencies is shown. Conclusions were made and recommendations were given regarding the use of the considered methods taking into account the properties of the measurement objects. References 16.

Electrode module for EIT with a robust howland current source

Electrical Impedance Tomography (EIT) is a non-invasive imaging technique that reconstructs internal conductivity distributions of a body from electrical measurements taken on its boundary. This study contributes to the field by focusing on the technological intricacies of absolute EIT imaging, which is challenged by limitations such as the resolution capacity of the hardware and the complexities introduced by imaging capacitive bodies. The novel EIT system architecture proposed enhances the accuracy of measurement by integrating current sources and Analog-to-Digital Converters (ADCs) closer to the electrodes, employing alternating current excitations to accurately capture phase information. This system uses a dynamic arrangement of surface electrodes that continuously alter their roles between current injection and voltage measurement, in a synchronized sequence, to ensure the accuracy of the measurements. The paper describes the design and implementation of both the excitation and measurement subsystems, highlighting the use of digital signal demodulation near the electrode to reduce data transfer issues. Experimental results confirm the system’s capability for real-time image reconstruction at 50 frames per second with precision in phase delay measurements, suggesting significant potential for clinical and industrial applications. Future work will aim to further refine signal generation with higher-speed DACs and expand to image reconstruction with more channels.

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

Real-time generation of circular patterns in electron beam lithography

Electron beam lithography (EBL) involves the transfer of a pattern onto the surface of a substrate by first scanning a thin layer of organic film (called resist) on the surface by a tightly focused and precisely controlled electron beam (exposure) and then selectively removing the exposed or nonexposed regions of the resist in a solvent (developing). It is widely used for fabrication of integrated circuits, mask manufacturing, photoelectric device processing, and other fields. The key to drawing circular patterns by EBL is the graphics production and control. In an EBL system, an embedded processor calculates and generates the trajectory coordinates for movement of the electron beam, and outputs the corresponding voltage signal through a digital-to-analog converter (DAC) to control a deflector that changes the position of the electron beam. Through this procedure, it is possible to guarantee the accuracy and real-time control of electron beam scanning deflection. Existing EBL systems mostly use the method of polygonal approximation to expose circles. A circle is divided into several polygons, and the smaller the segmentation, the higher is the precision of the splicing circle. However, owing to the need to generate and scan each polygon separately, an increase in the number of segments will lead to a decrease in the overall lithography speed. In this paper, based on Bresenham’s circle algorithm and exploiting the capabilities of a field-programmable gate array and DAC, an improved real-time circle-producing algorithm is designed for EBL. The algorithm can directly generate circular graphics coordinates such as those for a single circle, solid circle, solid ring, or concentric ring, and is able to effectively realizes deflection and scanning of the electron beam for circular graphics lithography. Compared with the polygonal approximation method, the improved algorithm exhibits improved precision and speed. At the same time, the point generation strategy is optimized to solve the blank pixel and pseudo-pixel problems that arise with Bresenham’s circle algorithm. A complete electron beam deflection system is established to carry out lithography experiments, the results of which show that the error between the exposure results and the preset patterns is at the nanometer level, indicating that the improved algorithm meets the requirements for real-time control and high precision of EBL.

Study on low power ADC Design using Memristor on Embedded systems

As portable and battery-operated devices become more common, embedded systems must meet the highest standards for low power consumption. Conventional analog-to-digital converters (ADCs) add a substantial amount of power to these systems overall. The design and application of low power ADCs using memristor technology are examined in this work. Memristors present a viable substitute for traditional ADC components because of their high density and non-volatile memory capabilities. Through the utilization of memristors' special qualities—like their low voltage operation and powerlessness—this research attempts to create ADC architectures with much lower power consumption. The suggested design creates a small, effective, and power-saving solution by integrating memristors in the analog front end and digital processing stages of the ADC. According to experimental results, memristor-based ADCs can save a significant amount of power without sacrificing performance, which makes them perfect for next-generation embedded systems applications. By advancing the design of energy-efficient embedded systems, this study may prolong the lifespan of portable electronics and open up new applications in wearable and Internet of Things (IOT) technologies.

A 0.012‐mm2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor

SummaryThis paper proposes a true random number generator (TRNG) based on a successive approximation register (SAR) analog‐to‐digital converter (ADC). A top‐plate sampling SAR ADC structure and a new MSB‐isolation switch scheme (MISS) are combined to achieve low‐power operation and small area occupancy at the same time. When the SAR ADC has completed its conversion, a secondary firing of the comparator measures the remaining signal. This 1‐bit quantized residue serves as the true random sequence, thus eliminating the need for extra circuitry in the TRNG. A 65‐nm prototype of the proposed TRNG was found to occupy an area of 0.012 mm2 and successfully passed all the National Institute of Standards and Technology (NIST) tests without post‐processing. It achieved a figure‐of‐merit of 0.244 pJ/bit for a 1 Mb/s random sequence with a 0.8‐V power supply. Its resilience to power noise injection attacks was also verified.

Sleep disturbances, cognitive decline, and AD biomarkers alterations in early Parkinson's disease.

We aimed to investigate whether each type of sleep disturbances (i.e., pRBD, EDS, and insomnia) is specifically associated with faster decline in global cognition and different cognitive domains among de novo PD patients. We also assessed the influence of sleep disturbances on core AD CSF biomarkers alterations and conversion to dementia. Prospectively longitudinal data were obtained from the PPMI cohort. Sleep disturbances and cognition ability were assessed by questionnaires at baseline and follow-up visits. Generalized linear mixed models were utilized to assess the effect of sleep disturbances on cognitive decline and core AD CSF biomarkers change. The associations between sleep disturbances and conversion to dementia were analyzed using Cox regression analysis. Baseline pRBD was associated with faster decline in global cognition and all cognitive domains, including verbal episodic memory, visuospatial ability, executive function, language, and processing speed. EDS was associated with faster decline in three cognitive domains, including verbal episodic memory, executive function/working memory, and processing speed. Insomnia was associated with faster decline in global cognition and verbal episodic memory. Meanwhile, pRBD and EDS were associated with longitudinal decrease of CSF Aβ42. Baseline pRBD increased the risk of conversion to dementia. The risk of dementia in PD patients with multiple sleep disturbances also increased compared with those without sleep disturbance. Sleep disturbances (i.e., pRBD, EDS, and insomnia) were associated with cognitive decline in early PD. EDS and pRBD were associated with decrease of CSF Aβ42. Moreover, pRBD was associated with conversion to dementia.

A Two-Year Observational Study to Evaluate Conversion Rates from High- and Low-Risk Patients with Amnestic Mild Cognitive Impairment to Probable Alzheimer's Disease in a Real-World Setting.

Predicting conversion to probable Alzheimer&s disease (AD) from amnestic mild cognitive impairment (aMCI) is difficult but important. A nomogram was developed previously for determining the risk of 3-year probable AD conversion in aMCI. To compare the probable AD conversion rates with cognitive and neurodegenerative changes for 2 years from high- and low risk aMCI groups classified using the nomogram. This prospective, multicenter, observational study was conducted in Korea. A total of patients were classified as high- or low-risk aMCI according to the nomogram and followed-up for 2 years to compare the annual conversion rate to probable AD and brain structure changes between the two groups. In total, 176 (high-risk, 85; low-risk, 91) and 160 (high-risk, 77; low-risk, 83) patients completed the 1-year and 2-year follow-up, respectively. The probable AD conversion rate was significantly higher in the high-risk (Year 1, 28.9%; Year 2, 46.1%) versus low-risk group (Year 1, 0.0%; Year 2, 4.9%, both p < 0.0001). Mean changes from baseline in Seoul Neuropsychological Screening Battery-Dementia Version, Clinical Dementia Rating-Sum of Box, and Korean version of the Instrumental Activities of Daily Living scores and cortical atrophy index at Years 1 and 2 were significantly greater in the high-risk group (p < 0.0001). The high-risk aMCI group, as determined by the nomogram, had a higher conversion rate to probable AD and faster cognitive decline and neurodegeneration change than the low-risk group. These real-world results have clinical implications that help clinicians in accurately predicting patient outcomes and facilitating early decision-making.Trial Registration: ClinicalTrials.gov (NCT03448445).

A neural network‐based error correction in the first‐stage residue of pipelined analog to digital converters

SummaryAn analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs.

Microcontroller-Optimized Measurement Electronics for Coherent Control Applications of NV Centers.

Long coherence times at room temperature make the NV center a promising candidate for quantum sensors and quantum computers. The necessary coherent control of the electron spin triplet in the ground state requires microwave π pulses in the nanosecond range, obtained from the Rabi oscillation of the mS spin states of the magnetic resonances of the NV centers. Laboratory equipment has a high temporal resolution for these measurements but is expensive and, therefore, uninteresting for fields such as education. In this work, we present measurement electronics for NV centers that are optimized for microcontrollers. It is shown that the Rabi frequency is linear to the output of the digital-to-analog converter (DAC) and is used to adapt the time length π of the electron spin flip, to the limited pulse width resolution of the microcontroller. This was achieved by breaking down the most relevant functions of conventional laboratory devices and replacing them with commercially available integrated components. The result is a cost-effective handheld setup for coherent control applications of NV centers.

Oxide semiconductor based deep‐subthreshold operated read‐out electronics for all‐printed smart sensor patches

AbstractThe ability to fabricate an entire smart sensor patch with read‐out electronics using commercial printing techniques may have a wide range of potential applications. Although solution‐processed oxide thin film transistors (TFTs) are capable of providing high mobility electron transport, resulting in large ON‐state current and power output, there is hardly any literature report that uses the printed oxide TFTs at the sensor interfaces. Here, printed amorphous indium‐gallium‐zinc oxide (a‐IGZO)‐based deep‐subthreshold operated TFTs that comprise signal amplifiers and analog‐to‐digital converters (ADCs) that can successfully digitalize the analog sensor signals up to a frequency range of 1 kHz are reported. In addition, exploiting the high current oxide TFTs, a current drive circuit placed after the ADC unit has been found useful in producing easy‐to‐detect visual recognition of the sensor signal at a predefined threshold crossover. Notably, the entire smart sensor patch is demonstrated to operate at a low supply voltage of ≤2 V, thereby ensuring that it can be an on‐chip energy source compatible and standalone detection unit.

A phase modulation method of sine signal for dual-active-valve piezoelectric pump

A phase modulation method with wide range and high resolution for the sine signal is essential for dual-active-valve piezoelectric pump (DAVPP) control. In DAVPP, by phase modulation, the flow direction can be changed and the output flow rate and pressure can be precisely adjusted. In this article, the authors developed a phase modulation method for the sine signal. This method is characterized by both the combination of hardware and software, and the combination of digital circuits and analog circuits. In hardware, a sinxcosϕ constructing circuit and a cosxsinϕ constructing circuit are specially structured, which enables phase modulation to be achieved. In software, the output phase is determined by the digital controlling quantities sent by the main control chip and stored in the form of a table. Analytical formulas for the cosine constructing table tab_cos and the sine constructing table tab_sin are analyzed and structured. Experimental results show that the output phase can be regulated linearly and continuously, within a range of 0°–360°. Its resolution can be improved according to the requirements. Although the modulation process and circuit are simple, it can effectively solve the problem of sine signal phase modulation for DAVPP control.

Fast switching hydrogen gas leakage identification using FPGA

Hydrogen will play a key part in the decarbonization of the global energy supply as the wealth of hydrogen continues to rise. However, applying hydrogen knowledge necessitates the installation of strong safety protocols, including the use of reliable hydrogen gas-detecting devices. Gas detection and monitoring at a large scale in industries need programmable electronic systems that can provide fast response and switching. The objective of the research work is to analyze the hydrogen gas detection system using a field programmable gate array (FPGA). The system is integrated with the gas sensor module, temperature control module, buzzer for alarm, liquid crystal display (LCD) and light-emitting diode (LED) for information display, and global system for mobile communication (GSM) for wireless message communication to the mobile. The temperatures module works on the sampling of the heater resistance using a voltage divider and inbuilt analog-to-digital converter (ADC), which depend on the output voltage of the digital-to-analog converter (DAC). The comparator module compares the gas concentration with the pre-decided threshold limit and acknowledges the buzzer accordingly. The system behavior for monitoring and gas concentration detection is simulated in Xilinx Vivado design suite 2020.1. The functionality of the chip is also verified in the Modelsim 10.0 waveform simulator. for the testbench tata sand samples used. LCD (16x2) displays the messages whether hydrogen gas is detected or not and the same message is delivered on mobile. The novelty of the work is that the system is applicable for faster switching in industrial applications and the designed system supported 550 MHz frequency in our simulation and synthesis.

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.