Digital Switching Noise Research Articles

Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction

Spread spectrum clocking (SSC) conventionally uses frequency modulation (FM) to suppress digital switching noise in the frequency domain. While clock-FM effectively reduces spectral noise peaks, it maintains the synchronous operation per cycle with total noise unchanged. In this paper, we introduce plesiochronous design as a general applicable de-synchronization solution for the spectral switching noise optimization with guaranteed quality-of-service. By modeling on-chip aperiodic supply current as a poly-cyclostationary random process, we theoretically prove that digital plesiochronous design contributes to reducing both, total and peak switching noise, in a harmonic frequency band of interest logarithmically proportional to the number of adopted clock domains over the synchronous baseline. A complete framework is also developed to implement plesiochronous design with the optimal clock domain partitioning and FIFO-based synchronization that features a minimum depth of six by employing Johnson encoding fully compatible with mainstream design flow. Validated on a 130nm pipelined FFT test chip across 25 dies thus taking process variations into account, our plesiochronous SSC achieves on average 5.1dB total power reductions in addition to 12.8dB peak power reductions of substrate noise at the clock fundamental frequency, which match our predictions, with only marginal hardware overhead in terms of cell area and power consumption.

A GALS design based on multi-frequency clocking for digital switching noise reduction

In this paper, we investigate two design techniques to reduce the digital switching noise on the power supply lines: a multi-frequency clocking (MFC) and a globally asynchronous locally synchronous (GALS) design technique. By deploying an MFC design, we can spread the switching current peaks over a frequency band, which results in the supply noise reduction. With the use of a GALS technique, we partition a large synchronous design into some smaller locally synchronous modules (LSMs) which are clocked by their own local clocks. Each local clock signal can be different from the other in terms of frequency or phase. Thus, we can also distribute the digital switching activities inside circuits over time, which leads to the supply noise reductions. The experimental results on a commercial Field Programmable Gate Array (FPGA) Spartan-3 (XC3S400-TQ144) show that the noise reduction rates can be achieved up to 17.4 dB for a GALS system with 8 LSMs, and 19.2 dB for the joint use of the MFC and GALS techniques with 4 LSMs. Moreover, as a real design example, a DES crypto processor with the deployment of GALS design and multi-frequency clocking strategy is also implemented and evaluated. The noise reduction rate is achieved about 19.5 dB at the fundamental frequency.

Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions

This paper presents a methodology for digital switching noise suppressions on the power lines at a fundamental frequency as well as its harmonics by using a clock scheduling technique in the frequency domain. Our approach provides a deep insight of the clock scheduling at the arbitrary phase shifts of clock signals. Moreover, an optimization algorithm is applied to find an optimal phase shift of a clock signal in order to maximize noise suppressions at a specific frequency band. The experimental results on a Xilinx field-programmable gate array Spartan-3 (XC3S400-TQ144) show that the estimated noise reduction rates well-match the measured ones. In these tests, dummy logics are used as noise injectors. This paper also presents a design example with a data encryption standard cryptoprocessor to demonstrate the applicability of our approach. The experiments show that the highest error between the estimated and the measured results is about 2.5 dB. Interestingly, our approach seems to be appropriately used with the designs in wireless communications where designers address to minimize the digital switching noise at the specific frequency bands of interest.

Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling

The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency.

A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

A stacked field-effect transistor (FET) linear cellular antenna switch adopting a transistor layout with odd-symmetrical drain–source metal wiring and an extremely low-power biasing strategy has been implemented in silicon-on-insulator CMOS technology. A multi-fingered switch-FET device with odd-symmetrical drain–source metal wiring is adopted herein to improve the insertion loss (IL) and isolation of the antenna switch by minimizing the product of the on-resistance and off-capacitance. To remove the spurious emission and digital switching noise problems from the antenna switch driver circuits, an extremely low-power biasing scheme driven by only positive bias voltage has been devised. The proposed antenna switch that employs the new biasing scheme shows almost the same power-handling capability and harmonic distortion as a conventional version based on a negative biasing scheme, while greatly reducing long start-up time and wasteful active current consumption in a stand-by mode of the conventional antenna switch driver circuits. The implemented single-pole four-throw antenna switch is perfectly capable of handling a high power signal up to $+$ 35 dBm with suitably low IL of less than 1 dB, and shows second- and third-order harmonic distortion of less than $-$ 45 dBm when a 1-GHz RF signal with a power of $+$ 35 dBm and a 2-GHz RF signal with a power of $+$ 33 dBm are applied. The proposed antenna switch consumes almost no static power.

Highly Linear Silicon-on-Insulator CMOS Digitally Programmable Capacitor Array for Tunable Antenna Matching Circuits

A stacked-FET linear 4-bit silicon-on-insulator (SOI) CMOS switched capacitor array is designed for use in tunable antenna matching circuits. A New biasing strategy without negative bias voltage is proposed to circumvent drawbacks such as digital switching noise and harmonics feed-through to the antenna. The proposed switched capacitor array shows almost identical power handling capability to that of the conventional version with negative bias voltage. Compared to other works in SOI or silicon-on-sapphire (SOS) technologies, it shows a comparable or better quality factor, tuning range, power handling capability, and harmonic distortion while consuming ultra low power.

Virtual Ground Fence for GHz Power Filtering on Printed Circuit Boards

In mixed-signal systems, noise coupling between different domains, such as digital and RF, can be a critical problem. Especially, the power/ground planes in packages or boards can be a major factor for noise coupling. Simultaneously switching drivers causes supply voltage fluctuations which can propagate both horizontally and vertically between the power/ground planes. The sensitive RF/analog signals have to be isolated from this digital switching noise, which gets coupled through the shared power distribution system. Hence, accurate estimation and improvement of the performance of power/ground planes is critical in a mixed-signal system. This paper introduces a new methodology to minimize the transfer impedance of the power distribution system. This will be achieved by a new design methodology, called the virtual ground fence. At its basic level, the virtual ground fence consists of quarter-wave transmission line stubs that act as short circuits between power and ground planes at their design frequency. An array of such stubs can then be considered as a ground fence. Power filtering is currently achieved mainly by using discrete decoupling capacitors at low frequencies. The virtual ground fence design is the distributed analog of this methodology at the gigahertz frequency regime.

A Design Technique for Embedded Electromagnetic Band Gap Structure in Load Board Applications

A new design technique and analysis for an embedded electromagnetic bandgap (EBG) structure is presented. In modern multifunction designs, it may be required to integrate noise-sensitive analog circuits next to digital circuits. Here, digital switching noise can propagate through power/ground planes and affect analog circuit performance. It is important to block this effect. To prevent the noise propagation, an EBG-patterned power/ground plane can be an acceptable solution. However, difficulties arise when the EBG structure is put in a stripline-like environment; the embedded EBG structure loses the noise filtering function. The reason for the functional failure is analyzed, followed by a solution. The proposed solution has been demonstrated by both simulation and measurement. Simulation and measurement results demonstrate that the proposed embedded EBG structure can be effective for the desired noise isolation. The design technique is tested on a prototype load board for a 10-bit 3-GHz analog-to-digital converter from National Semiconductor. The suggested design technique for the embedded EBG structure includes three design parameters: 1) the potentials of the planes above and below the EBG layer; 2) the thicknesses of the dielectric layers above and below the EBG layer; and 3) the number and position of vias interconnecting the top and bottom planes.

A New Grounding Scheme to Reduce the Electromagnetic Emission of Smart-Power System-on-Chips

This paper focuses on the electromagnetic emissions of smart-power integrated systems that include analog, digital, and power sections. With reference to common high-voltage CMOS technology processes, it is shown that the switching noise of digital core blocks can propagate to the power sections through the silicon substrate they share. Such disturbances feed the printed circuit board traces and cables connected to the IC power section, which behave like parasitic antennas, and unwanted electromagnetic emissions are experienced. A generic integrated system fabricated with a planar CMOS technology process is considered and the propagation of digital switching noise is analyzed referring to a system level equivalent circuit, which comprises a substrate model and an IC package model. Based on this, the circuit parameters that affect the propagation of the switching noise are highlighted and a new grounding scheme, which reduces the substrate parasitic coupling in smart-power system-on-chip, is proposed. Its effectiveness is proved through computer simulations and experimental tests.

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to the current pulses drawn from voltage supplies in mixed analog-digital CMOS ICs. To this end, two test chips were designed in 0.18-μm CMOS technology. The two test chips were integrated and then mounted on a board with and without package to compare measurements on chips mounted in package and mounted on board. To ensure that the differences between measurements are only due to the assembling technique, the same printed circuit boards were used for both chip-in-package and chip-on-board. Moreover, the experimental setup was carefully arranged so as not to introduce further disturbances due to external connections or noise sources. Both ICs were extensively simulated by using a realistic model of on-chip and off-chip parasitics to study what happens in the analog section when digital switching noise is injected. Simulations results, confirmed by test chip measurements, demonstrate that disturbances due to switching currents in digital blocks propagate through substrate, package, and interconnection parasitics and affect analog voltages, thus degrading the circuit performance. Therefore, reduction of parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends.

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. In addition, it can calibrate the CP under different control voltages on the loop filter to be immune to the channel-length modulation. Due to the digital nature, the additional power consumption and digital switching noise from the calibration circuits are turned off once the calibration is finished. A 5 GHz frequency synthesizer is used to justify the proposed calibration technique. The measured output spur is suppressed by 5.35 dB at 5.2 GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110 dBc/Hz at an offset frequency of 1 MHz.

A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications

In system-on-chip applications, the digital switching noise propagates through substrate and power distribution to analog circuits, degrading their performance. To monitor and analyze the digital switching noise coupling, small and compact sensors that can be embedded within high-density circuits are essential. This paper presents PMOS-based differential substrate and power-supply sensors and an on-chip waveform sampler, which focus on wide bandwidth, reduced parasitic interactions, and small compact size. The bandwidth of the proposed sensors, which is implemented with an IBM 0.13- CMOS technology, is useful from DC to 1.6 GHz. Linearity is better than 1.5% for substrate and 6% for power-supply sensors. Power-supply rejection of 64 dB has been achieved in the substrate probing. The substrate noise coupling into the power-supply probing was below detectable limits. Experimentally reconstructed waveforms with 20-ps time resolution allowed the measurement of amplitude, rise time, and overshoot of transition edges.

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-/spl mu/m CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanisms behind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design.

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.

5-6 GHz SiGe active I/Q subharmonic mixers with power supply noise effect characterization

A 5-6 GHz active subharmonic I/Q mixer pair has been designed and fabricated for use in direct conversion receivers for the Unlicensed National Information Infrastructure (U-NII) bands. The design includes I and Q subharmonic mixers and an LO conditioning chain. All circuits are fully differential and are designed to operate from a 3.3 V supply. Each mixer consumes 5 mA of current. A conversion gain of 6 dB, an IIP2 of +29 dBm and an input 1-dB compression point of -5.4 dBm were measured. The 90/spl deg/ phase balance between the I and Q mixer IF outputs was investigated in the presence of injected digital switching noise on the power supply lines; 90/spl deg/ balance was maintained over a wide range of switching waveform frequencies and amplitudes.

Delay-insensitive logic in software-defined radio applications

This article describes how one of the fundamental hardware stumbling blocks to fully achieving software-defined radio, high speed, and wide dynamic range data conversion can be overcome with the selective application of a class of asynchronous logic referred to as delay-insensitive logic. Certain characteristics of delay-insensitive logic can be exploited using unique architectures to reduce digital switching noise and whiten the noise signature. The result is enhanced mixed mode performance in highly integrated systems. The performance enhancement of an interpolating digital-to-analog converter is presented as a specific example. Because the concept of delay-insensitive logic is not familiar to most engineers, a brief introduction to the general concept is given.

Design of low-phase-noise CMOS ring oscillators

This paper presents a framework for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset frequencies. We define the effective Q factor for ring oscillators with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes.

Measurements and analysis of PLL jitter caused by digital switching noise

When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-/spl mu/m digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons.

Partitioning Analog and Digital Processing in Mixed-Signal Systems

Shrinking feature sizes, combined with the need for low-power and lightweight components, fuel the desire to place large mixed-signal systems onto a single die. A major design issue in mixed-signal systems is the effect of digital switching noise coupled to sensitive analog circuits through the substrate. A method is presented for minimizing this effect by partitioning digital and analog processing into separate time blocks. The resulting trade-off between lost signal and increased energy consumption is explored. As an example, a GPS synchronizer design is analyzed with respect to modifications that can be made to increase performance, while minimizing any associated energy penalty. Application of the partitioning method to other communications systems is discussed.

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.