Digital Standard Cell Library Research Articles

Countermeasures against Static Power Attacks

In recent years it has been demonstrated convincingly that the standby power of a CMOS chip reveals information about the internally stored and processed data. Thus, for adversaries who seek to extract secrets from cryptographic devices via side-channel analysis, the static power has become an attractive quantity to obtain. Most works have focused on the destructive side of this subject by demonstrating attacks. In this work, we examine potential solutions to protect circuits from silently leaking sensitive information during idle times. We focus on countermeasures that can be implemented using any common digital standard cell library and do not consider solutions that require full-custom or analog design flow. In particular, we evaluate and compare a set of five distinct standard-cell-based hiding countermeasures, including both, randomization and equalization techniques. We then combine the hiding countermeasures with state-of-the-art hardware masking in order to amplify the noise level and achieve a high resistance against attacks. An important part of our contribution is the proposal and evaluation of the first ever standard-cell-based balancing scheme which achieves perfect data-independence on paper, i.e., in absence of intra-die process variations and aging effects. We call our new countermeasure Exhaustive Logic Balancing (ELB). While this scheme, applied to a threshold implementation, provides the highest level of resistance in our experiments, it may not be the most cost effective option due to the significant resource overhead associated. All evaluated countermeasures and combinations thereof are applied to a serialized hardware implementation of the PRESENT block cipher and realized as cryptographic co-processors on a 28nm CMOS ASIC prototype. Our experimental results are obtained through real-silicon measurements of a fabricated die of the ASIC in a temperature-controlled environment using a source measure unit (SMU). We believe that our elaborate comparison serves as a useful guideline for hardware designers to find a proper tradeoff between security and cost for almost any application.

An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification

Real number models, which are computationally efficient analog functional models, are now indispensable in verifying complex mixed-signal systems on chip (SoCs); yet, creating and validating these models remain difficult. To remove this problem, we created a framework for building analog functional model templates. Each template covers a class of circuits (e.g., oscillators or amplifiers) and can generate functional models for any implementation of this circuit class, regardless of pin configurations, circuit topologies, and process technologies/corners. This ability to cover many implementations with one template allows one to create a “standard model template” library that covers all the basic analog building blocks used in mixed-signal SoCs. Like a digital standard cell library, this template library only contains the low-level building blocks. Models for more complex systems, such as a phase-locked loop, are constructed using a number of these models. Our template library also contains validation routines for each of the models, measuring the key performance parameters of the modeled function. These routines can also be used to drive the circuit-level implementation of this function, making it easy to update the parameters of the functional models to match their circuit implementations. We demonstrate the utility of our template library on several mixed-signal IPs integrated into an SoC. Using the proposed framework, designers can easily generate a working model of an analog functional block in a second and thus construct a complete mixed-signal IP model for the design exploration in less than a couple of hours, while it typically needs a few days when the models are manually written. The regeneration of the models to reflect the behaviors of real implementations can be seamlessly done in less half a day from the same template library. In addition to the vast improvement in model creation speed, the generated model from the template library is less error-prone by archiving designer’s experience from previous mistakes to the template library.

A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD

In this letter, a fully synthesizable injection-locked phase-locked loop (IL-PLL) is presented. The proposed PLL employed a nonmodified digital standard cell library, and enable fast design migration to other processes. To minimize the reference spur, a self-clocked nonoverlap update scheme is proposed to reduce the reference spur caused by digital logic clocking. Besides, a slope-balanced fully symmetrical multiplexer (MUX) and subsampling bang–bang phase detector (SS-BBPD) is proposed. With constraint-directed automatic layout synthesis, the delay offset is greatly reduced. Implemented in a 65-nm CMOS process, the PLL achieved a 0.4-ps integrated jitter at 1-GHz output frequency with −52-dBc reference spur. The power consumptions are 1.2 mW, corresponding to figures of merit of −247.2 dB.

Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library

In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8[Formula: see text]V by using Silvaco’s EDA tools. All generated cells have same cell height of 1.58 [Formula: see text]m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS’85 benchmark circuits 74181 and c17 are designed and verified with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications.

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

This paper presents a standard-cell-based semiautomatic design methodology for a new conceptual countermeasure against electromagnetic (EM) analysis and fault-injection attacks. The countermeasure, called the EM attack sensor, utilizes LC oscillators that react to variations in the EM field around a cryptographic LSI caused by a microprobe brought near the LSI. A dual-coil sensor architecture with digital calibration based on lookup table programming can prevent various microprobe-based EM attacks that cannot be thwarted by conventional countermeasures. All components of the sensor core are semiautomatically designed by standard electronic design automation tools with a fully digital standard cell library and hence minimum design cost. This sensor can therefore be scaled together with the cryptographic LSI to be protected. The sensor prototype is designed based on the proposed methodology together with a 128-bit-key composite AES processor in 0.18-$$\upmu \hbox {m}$$μm CMOS with overheads of only 2 % in area, 9 % in power, and 0.2 % in performance, respectively. The countermeasure has been validated against a variety of EM attack scenarios. In particular, some further experimental results are shown for a detailed discussion.

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

A multiplexer-based digital passive linear counter (PLINCO)

A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n 2 for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded passive linear counter also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.

A digitally controlled PLL for SoC applications

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.

A portable clock multiplier generator using digital CMOS standard cells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 /spl mu/m CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps.