A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD

Abstract

In this letter, a fully synthesizable injection-locked phase-locked loop (IL-PLL) is presented. The proposed PLL employed a nonmodified digital standard cell library, and enable fast design migration to other processes. To minimize the reference spur, a self-clocked nonoverlap update scheme is proposed to reduce the reference spur caused by digital logic clocking. Besides, a slope-balanced fully symmetrical multiplexer (MUX) and subsampling bang–bang phase detector (SS-BBPD) is proposed. With constraint-directed automatic layout synthesis, the delay offset is greatly reduced. Implemented in a 65-nm CMOS process, the PLL achieved a 0.4-ps integrated jitter at 1-GHz output frequency with −52-dBc reference spur. The power consumptions are 1.2 mW, corresponding to figures of merit of −247.2 dB.