Abstract
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0dBc, and the reference spur is -64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of -240.4dB and -245.5dB.
Highlights
A S CMOS processes reach sub-20nm scales, various challenges complicate the analog/mixed-signal circuit design, such as low supply, high variations and limited model accuracy [1]
A robust digital nonlinearity calibration that is suitable for the synthesizable DTC is proposed
The core area of the multiplying delay-locked loop (MDLL) is 0.126 mm2, which is fabricated in TSMC 65 nm LP CMOS process
Summary
Bangan Liu , Member, IEEE, Yuncheng Zhang , Graduate Student Member, IEEE, Junjun Qiu, Graduate Student Member, IEEE, Huy Cu Ngo , Member, IEEE, Wei Deng , Senior Member, IEEE, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang , Member, IEEE, Aravind Tharayil Narayanan , Senior Member, IEEE, Haosheng Zhang , Member, IEEE, Teruki Someya , Member, IEEE, Atsushi Shirane, Member, IEEE, and Kenichi Okada , Senior Member, IEEE. Abstract— In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop (MDLL) is presented. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Teruki Someya is with the Electronic Instrumentation Laboratory, Delft University of Technology, 2628 Delft, The Netherlands. Color versions of one or more of the figures in this article are available online at https://ieeexplore.ieee.org
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