Digital Signal Processing Research Articles

Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic

Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode MAC block supports three modes of operation; single 64-bit MAC operation, dual 32-bit multiplication with 32-bit single addition, and single 32-bit MAC operation. The design has utilized an adjusted architecture for the Vedic-multiplier (Adjusted-VM), a 64-bit HBK-CSLA, and a control circuit to select the desired mode of operation. The performance of the multi-mode MAC is then optimized by exploiting pipelining concept. The proposed architectures are synthesized in various FPGA families utilizing VHDL language in Xilinx ISE14.7 tool. The performance results have exposed that the proposed 64-bit I-MAC block have attained observable lessen 9.767% in delay and area usage of 47.49% compared with the most existing MAC block designs.

Temperature compensation study of pressure sensors after leadless packaging

Purpose The purpose of this paper is to reduce the problem of temperature drift causing output errors in such sensors, three hardware compensation schemes are proposed in this paper, and three compensation schemes are designed and implemented. Design/methodology/approach In response to the problem of temperature drift causing output errors in this type of sensor, this paper proposes three hardware compensation schemes and carries out the design and implementation of the three compensation schemes. Finally, the advantages and disadvantages of the three compensation schemes are discussed through the analysis of the experimental results. The three hardware compensation methods are series-parallel resistance network compensation, digital signal processor (DSP) compensation and the joint compensation of resistance network and DSP. Series parallel resistance network compensation is to connect the low-temperature drift resistance and the sensor in series and parallel; DSP compensation is based on the combination of cubic spline interpolation and linear fitting algorithm, which uses DSP to process the data. Joint compensation is a new compensation method composed of the above two compensation methods. Findings The experimental results show that the relative error of the output is reduced to a certain extent after the three compensation methods, and the relative error of the output after the joint compensation is reduced to about 0.2%, which proves that the three compensation methods are feasible. Originality/value This paper presents three novel hardware compensation methods to reduce temperature drift in silicon on insulator (SOI) high-temperature pressure sensors. The joint compensation method, combining resistance network and DSP compensation, is particularly innovative and significantly improves output accuracy, reducing relative error to about 0.2%.

Hybrid multi-objective optimization of µ-synthesis robust controller for frequency regulation in isolated microgrids

Frequency regulation in isolated microgrids is challenging due to system uncertainties and varying load demands. This study presents an optimal µ-synthesis robust control strategy that regulates microgrid frequency while enhancing system performance and stability—a proposed fixed-structure approach for selecting performance and robustness weights, informed by subsystem frequency analysis. The controller is optimized using multi-objective particle swarm optimization (MOPSO) and multi-objective genetic algorithm (MOGA) under inequality constraints, employing a Pareto front to identify optimal solutions. Comparative analyses demonstrate that the MOPSO-optimized controller achieves superior robustness and performance, tolerating up to 236% uncertainty compared to 171% for conventional µ-synthesis controllers. Additionally, it significantly reduces frequency deviation and enhances transient response. Nyquist stability analysis confirms robustness across renewable energy uncertainties. The results highlight the proposed controller’s effectiveness in isolated microgrid frequency regulation, with future work focused on discrete-time implementation for practical digital signal processing (DSP) applications.

Digitizing Low-Frequency Analog Control Circuit Using Bilinear Function Algorithm

In the past, low-frequency analog control circuits were largely used in analog control systems. With the rapid development of modern digital electronic technology, the digitization of traditional low-frequency analog control circuits while retaining the same functions as the original analog control systems has become an important trend in the field of electronic design. For this reason, this study aimed to develop an analog signal digitization model for control signals at a low frequency below 10 Hz. In terms of signal receiving and transmission requirements, the proposed model is configured with analog-to-digital converter (ADC), digital-to-analog converter (DAC), and pulse width modulation (PWM) functions. In the development environment, the input and output signals are first normalized and processed with PWM, enabling the digital signal processor to deal with analog signal receiving, processing, and external transmission. To replace the existing compensator in analog circuits, a digital compensator is used in the digital signal processor. Based on the bilinear function in MATLAB software, the parameter values demanded for the digital compensator can thus be obtained, achieving the automatic calculation of bilinear transformation in the system. Multisim simulation is then used to simulate analog circuit systems for comparison with the digitized outcomes. The experimental results reveal that the performance of the designed digital control circuit matches the simulation outcomes in both Bode gain (dB) and phase responses when the signal frequency is below 10 Hz. The effectiveness of the digitized analog control circuit for low-frequency control signals is therefore confirmed.

Theory of Faults (ToF): Numerical Quality Management in Complex Systems

The purpose of this manuscript is to provide general system theory concepts and practical tools for management under complexity. Built environments and infrastructure are produced, operated, and maintained by information systems; they are also integral components of information systems themselves. These systems are self-organized and teleonomic. The complexity inherent in built environments and infrastructure systems poses a challenge to research, hindering forecasting and the implementation of managerial tools. The use of faults, which are complex systems’ responses to penetrating risk, provide us with databases of and windows into complex systems. This manuscript presents an explicatory theory (ToF), develops it mathematically, expands it through numerical experiments, validates it by case studies, and relates it to practice by expert contributions. A statistical analysis provides a phase parameter, descriptive statistics elucidate trending and emergent behaviors, digital signal processing expounds the effects of signals on information overload, and a directed-network analysis portray morphology, entropy, and time effects. The novelty of ToF is in the application of complexity theory to construction to produce data analysis tools and a managerial framework.

Edge intelligence for poultry welfare: Utilizing tiny machine learning neural network processors for vocalization analysis.

The health of poultry flock is crucial in sustainable farming. Recent advances in machine learning and speech analysis have opened up opportunities for real-time monitoring of the behavior and health of flock. However, there has been little research on using Tiny Machine Learning (Tiny ML) for continuous vocalization monitoring in poultry. This study addresses this gap by developing and deploying Tiny ML models on low-power edge devices to monitor chicken vocalizations. The focus is on overcoming challenges such as memory limitations, processing power, and battery life to ensure practical implementation in agricultural settings. In collaboration with avian researchers, a diverse dataset of poultry vocalizations representing a range of health and environmental conditions was created to train and validate the algorithms. Digital Signal Processing (DSP) blocks of the Edge Impulse platform were used to generate spectral features for studying fowl vocalization. A one-dimensional Convolutional Neural Network (CNN) model was employed for classification. The study emphasizes accurately identifying and categorizing different chicken noises associated with emotional states such as discomfort, hunger, and satisfaction. To improve accuracy and reduce background noise, noise-robust Tiny ML algorithms were developed. Before the removal of background noise, our average accuracy and F1 scores were 91.6% and 0.92, respectively. After the removal, they improved to 96.6% and 0.95.

Advanced Digital Signal Processing, Interpolation and Extrapolation Based Symmetrical Fault Assessment in Transmission Line

This article describes a novel method for locating and detecting triple line to ground (LLL-G) faults in 110 km of 132 kV transmission lines. To find the transmission line fault, the three phase system currents were first recorded at the appropriate sampling frequency. Then, the total harmonic distortion (THD) and direct current (DC) components were computed using the Fast Fourier transform (FFT). When compared to normal conditions, high values of THD and DC components have been seen in fault situations; fault has been identified as a result. The fault distance in the transmission line has been measured using spline extrapolation or linear interpolation. With this method, very encouraging outcomes have been obtained for fault assessment in transmission line.

Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier

Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method. This paper presents design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier. Urdhva Tiryagbhyam sutra has been used for multiplication purpose. The partial product addition in Vedic multiplier is realized using Brent Kung Adder. Simulation results shows that described Brent Kung Adder based 8-Bit Vedic Multiplier is efficiently decreases the Delay, power consumption and Area than other multipliers.

Algorithm for Detecting Reference Points on a Digital Electrocardiogram in Real Time

Relevance. The use of digital electrocardiographs and cardiac monitors with built-in algorithms for automatic processing, analysis and interpretation of electrocardiograms allows the doctor to effectively diagnose cardiac arrhythmias. It is known that in order to provide emergency care to a patient, the duration of arrhythmia diagnostics should not exceed several tens of seconds, which requires the emergence of new algorithms for detecting informative features indicating arrhythmia, operating in real time. The need to introduce new and effective technologies for diagnosing cardiovascular diseases is also reflected in public health development programmes.Research goal. Development and quality indicators analysis of the algorithm for reference points detection on a digital electrocardiogram, bearing informative signs for the procedure of arteries diagnosis.The methods used. The study is based on an analysis of existing approaches to the problem of reference points detection on digital electrocardiogram, as well as conducting a test of the proposed algorithms by mathematical modelling methods. The quality indicators of the algorithms defined in accordance with the principles of signal detection theory and diagnostic testing, at the junction of which the task of electrocardiogram reference point detection is located. The proposed algorithm was tested on materials of MIT-BIH Arrhythmia Database, which is widely used for verification and validation of real-time digital electrocardiogram signal processing algorithms.The results. The study proposes an algorithm for detecting reference points on a digital electrocardiogram that carry informative features for the arrhythmia diagnostic procedure. The proposed algorithm is based on digital signal filtering using a decision rule based on a three-step two-threshold principle of pre-processed electrocardiogram signal values comparison on a sliding window. An experiment on the materials of the open verified MIT-BIH Arrhythmia DB showed that the quality of the proposed algorithm for detecting reference points is higher than that of the algorithms used in modern digital electrocardiographs and cardiac monitors. The proposed algorithm based on digital signal filtering and the three-step two-threshold decision rule have elements of scientific novelty.The significance. The results of this work can be used in the development of digital heart rate monitors, cardiac devices and for automatic processing, analysis and real-time computer-assisted digital electrocardiogram signal interpretation.

The Resampling Methods Direct Sequence Spread Spectrum Signal’s Demodulator Implementation

Relevance. The direct spread spectrum signals are widely used in navigation and communication systems recently. These signals prevail in modern satellite navigation systems and are used in various communication systems with code division multiplexing in particularly. In this regard, the tasks of building direct spread spectrum signals’ demodulators have the key importance. Mach importance in the construction of demodulators is the problem chip rate variability.The purpose of the study is to propose a demodulator structure focused on solving this problem.Methods. The research is based on computer modeling methods.Decision. The paper proposes an approach to the construction of the direct spread spectrum signal’s demodulators based on modern methods of digital signal processing. It is shown that the main advantage of the proposed approach is the possibility of rebuilding the variable chip rate demodulators. Based on the results obtained, a scheme for the direct spread spectrum signals demodulator using resampling methods is proposed. Resampling, in turn, is implemented on the basis of polynomial interpolation using Lagrange polynomials. The structure of the resampler is proposed, similar to the structure of an interpolating filter with a finite impulse response. The presented simulation results show the effectiveness of the proposed approach.Novelty. It seems that the currently common methods of implementing direct spread spectrum signal in terms of delay synchronization do not sufficiently meet modern requirements. The implementation of delay synchronization schemes based on resampling is practically not discussed in well-known works. At the same time, modern methods and devices of digital signal processing make it possible to ensure an effective hardware implementation of the scheme in question. In this context, the approach proposed in the paper to the construction of demodulators seems to be very relevant.Significance. The results of the work can be used in the construction with direct spread spectrum signals’ demodulators for a wide range of communication and navigation systems. The synchronous sampling structure proposed in this paper is very promising, especially for variable chip rate demodulators.

A Study on the Application of FPGAs in Digital Signal Processing

Field-Programmable Gate Arrays (FPGAs) have emerged as a transformative technology in digital signal processing (DSP), offering unmatched flexibility, high performance, and real-time capabilities. This study explores the architecture of FPGAs, their integration with other digital systems, and the optimization methodologies that enhance their efficiency in diverse applications. From telecommunications and multimedia to biomedical and aerospace systems, FPGAs address the growing demand for adaptable, low-latency DSP solutions. The research highlights case studies, market trends, and future outlooks, demonstrating the pivotal role of FPGAs in shaping next-generation DSP technologies. By leveraging FPGA-specific features such as parallelism, pipelining, and dynamic reconfiguration, developers can meet the performance, efficiency, and scalability requirements of modern industries. The findings underscore the importance of continued innovation in FPGA-based DSP systems to drive advancements across emerging fields like AI, IoT, and autonomous systems. Keywords: FPGA, Digital Signal Processing (DSP), Real-Time Systems, Optimization Techniques, High- Performance Computing

Analysis and application of a 3D chaotic system with an extremely extensive range of amplitudes and offset boosting

Abstract The study of high-dimensional chaotic systems has been the subject of considerable research interest, whereas the complex characteristics of low-dimensional chaotic systems have been largely overlooked. A new dimensional (3D) chaotic system containing only two kinds of nonlinear terms is constructed based on the Lorenz system to enrich the theory of chaotic systems and improve the complex properties of low-dimensional chaotic systems. The system lacks a symmetric structure; however, under the influence of the symmetric parameter α, the system attains a symmetric state and can produce attractors with a symmetric structure. Under the parameter β, the system can realize the regulation of amplitude, frequency, and nonlinear offset boosting of three signals simultaneously. The parameter γ can realize the control of two signal amplitude and frequency at the same time. The system always remains chaotic when the parameters β and γ are varied in a great range. In addition, this 3D chaotic system has offset boosting behavior in arbitrary single and multiple directions, and the offset constant has a wide range of values. These features provide great convenience for secure communications and weak signal engineering applications. Further, analog circuit simulations and DSP (Digital Signal Processor) hardware circuits confirm the parametric modulation of the system and the offset boosting behavior in any direction. Moreover, taking advantage of the extensive offset range, a synchronization controller is designed for the drive and response systems. Finally, the modulation of offsets with a wide range of values realizes the encrypted transmission of binary digital information and lays the foundation for future engineering applications.

Low-loss weakly coupled four-mode hollow-core antiresonant fiber based on centrosymmetric nested structure

Abstract This paper designs a novel centrosymmetric double-layer nested antiresonant fiber (CDNAF) with few-mode transmission characteristics. The cladding structure of the CDNAF incorporates glass plates and multilayer capillaries, effectively mitigating the coupling between various core modes and cladding modes. Simulation results show that the CDNAF can support four modes of low-loss transmission from LP01 to LP02 at 1550 nm. The confinement loss (CL) of the four modes is less than 0.008 dB/km, 0.07 dB/km, 0.42 dB/km, and 4.8 dB/km, respectively, and the CDNAF has a sizeable differential group delay (DGD) and weak bending sensitivity. The loss of high-order modes is much greater than that of the other four transmission modes, ensuring high-purity transmission of the four modes. In the wavelength range of 1200–1700 nm, the CDNAF ensures few-mode characteristics with at least two low-loss transmission modes. Furthermore, the effective refractive index difference (Δneff) between adjacent modes is much greater than 10^(-4), eliminating or significantly reducing the need for multiple-input multiple-output digital signal processing (MIMO-DSP) techniques in optical communication systems. Additionally, the results demonstrate that CDNAF can transmit three modes at an ultimate bending radius of 5 cm and can transmit four modes like a straight fiber at a bending radius of 18 cm, which demonstrates that CDNAF has excellent bending performance. These excellent characteristics give the CDNAF great potential for application in large-capacity optical communication systems.

Advanced optimized detection scheme based on a neural network in a bandwidth-limited IM/DD system.

In this Letter, we propose a high-performance optimized detection scheme based on a neural network (NN) in a receiver digital signal processing (DSP) for bandwidth-limited intensity modulation and direct detection (IM/DD) transmission systems. The NN-based optimized detection scheme consists of two components, an NN-based lookup table (NN-LUT) and an NN-based log-maximum a posteriori estimation with a fixed number of surviving state (NN-MAP) decoder. The NN-LUT provides more accurate and sufficient a priori information (PI) to the decoder than the conventional filter-form PI without increasing computational complexity. The NN-MAP decoder can be optimized for detection using the NN-form PI. The proposed scheme is implemented in a 122-Gbps IM/DD optical 4-level pulse amplitude modulation (PAM-4) system with a 3.7-GHz 3-dB bandwidth. The results demonstrate that the proposed NN-MAP scheme can enhance receiver sensitivity by 1.4 dB under the same complexity compared to conventional optimized detection, achieving a 20% forward error correction threshold. To the best of our knowledge, this represents the inaugural instance of NN being employed for optimized detection.

Grid-Forming Fuel Cell System for an Islanded AC Grid

This paper proposes a two-stage converter that can black start an isolated AC Microgrid with a Fuel Cell (FC) as the primary energy source. The first stage is connected to the FC and employs a Three-Leg Interleaved Boost DC/DC Converter (IBC), while the second is a Three-Phase Voltage Source Converter (VSC). The DC/DC stage utilizes a Cascade Voltage Control (CVC) to mitigate voltage fluctuations in the DC-link caused by the variability of the FC voltage. For the DC/AC stage, three distinct grid-forming (GFM) strategies are implemented with two of them with multi-loop cascaded structure and one with a single-loop structure. The power circuit of the system is simulated using the Real-Time Simulator (RTS) HIL 602+ from Typhoon-HIL, with the control strategies embedded on the Digital Signal Processor (DSP) TMS320F28379D - F28379D LaunchPad from Texas Instruments (TI). The performance of the cases are verified through CHIL simulations for a balanced and unbalanced inductive load steps. The results demonstrate that for both tests the GFM single loop structure presents smoother transients and shorter recovery times. Additionally, for the unbalanced loads, all the cases present similar results for the DC variables with more pronounced differences at the AC side.

Enhancing Electric Bicycle Efficiency: Investigating Regenerative Braking and Pedal Charging Systems

Electric bicycles (e-bikes) are gaining global popularity as part of the broader shift towards electric vehicles (EVs). This research presents a regenerative electric bicycle designed to maximize energy efficiency, aiming for a top speed of 45 km/h and a range of 50 km. The bicycle incorporates two key energy recovery systems: a downhill regenerative system that captures braking energy and converts it into electricity, and a pedal charging system that converts pedaling kinetic energy to recharge the battery. A digital signal processing system seamlessly switches between charging and electric drive based on rider input. This study examines the effectiveness of these systems. The regenerative braking system achieved an impressive 30.9% efficiency in capturing energy during testing. The pedal charging system initially demonstrated an efficiency of 2.98%. MATLAB simulations revealed clear trends in force and power requirements across different grades (0°, 2.5°, 5°, 7.5°, and 10°), highlighting the crucial role of aerodynamic drag and gradient resistance in influencing performance and energy efficiency. While controlled testing environments require further real-world evaluation, these findings underscore the promising potential of regenerative braking and pedal charging for enhancing electric bicycle efficiency. This research paves the way for the development of more efficient and accessible electric bicycles, promoting sustainable transportation solutions through the selection of durable, efficient, and environmentally friendly components.

Novel Digital Signal Processing Method for Data Acquired From Low Coherence Interferometry

Novel Digital Signal Processing Method for Data Acquired From Low Coherence Interferometry

A perspective on digital signal processor based leadership performance accelerator for AI and HPC

A perspective on digital signal processor based leadership performance accelerator for AI and HPC

A Modular Step-Up DC/DC Converter for Electric Vehicles

A step-up DC/DC converter is required to match the fuel cell’s stack voltage with the DC-link capacitor of the propulsion system in fuel cell-based electric vehicles (FCEVs). Typically, the nominal voltage of a single fuel cell ranges from 0.5 V to 1 V, and the DC-link voltage usually lies between 400 V and 800 V. This article proposes a new modular step-up DC/DC converter capable of providing a wide voltage-boosting range from the input to the output side using series-connected isolated boosting submodules (SMs). Modified versions of boost and Cuk converters are designed and used as the SMs to deliver a flexible output voltage, combining the voltage-boosting capability with the ability to embed a medium/high-frequency transformer, which provides both galvanic isolation and an additional degree of voltage boosting while drawing a continuous input current from the fuel cell with minimal ripple, enhancing performance. The proposed modular converter offers the advantages of improved controllability, scalability, and greater reliability, particularly during partial faults. The feasibility of the proposed converter is demonstrated through computer simulations conducted using MATLAB/SIMULINK® R2024a software where a DC link of 400 V is created from 50 V input sources. Additionally, a 1 kW small-scale prototype is designed and controlled using a TMS320F28335 digital signal processor to validate the mathematical analysis and simulation results, where the SMs are controlled to create a DC link of 100 V from four 25 V input sources with an electrical efficiency of approximately 95%.

The Approximation of Functions of Several Variables with Bounded p-Fluctuation by Polynomials in the Walsh System

This paper presents direct and inverse theorems concerning the approximation of functions of several variables with bounded p-fluctuation using Walsh polynomials. These theorems provide estimates for the best approximation of such functions by polynomials in the norm of the space under consideration. The paper investigates the properties of the Walsh system, which includes piecewise constant functions, and builds on earlier work on trigonometric and multiplicative systems. The results are theoretical and have potential applications in such areas as coding theory, digital signal processing, pattern recognition, and probability theory.