TMS320C25 Digital Signal Processor Research Articles

Optimal Design of Hammerstein Cubic Spline Filter for Nonlinear System Modeling Based on Snake Optimizer

This work develops a new class of Hammerstein adaptive filters that contains a memory-less non-linear system followed by a linear adaptive filter, where the non-linear system comprises an adjustable look-up table (LUT) and a spline interpolator. This paper's first effort has been to employ the meta-heuristic algorithm (MHA) to the Hammerstein spline adaptive filter (HSAF), where it concurrently updates the weights of spline control points and linear filter based on the estimation problem. A novel MHA called snake optimiser algorithm (SOA) is used to enhance the assurance of convergence, estimated parameter accuracy and steady-state results. The presented experimental results indorse that the proposed SOA-based HSAF (SOA-HSAF) design exhibits more robust performance in dealing with higher degree non-linear systems under the Gaussian and Non-Gaussian circumstances compared to contemporary design methods like classical, some standard MHAs and other researchers reported techniques. The achieved simulation results are validated using a TMS320C6713 digital signal processor.

Tonic Pitch Estimation in South Indian Classical Music using DSP Processor

In South Indian Classical Music, a performer chooses the tonic pitch as the reference note throughout the performance. The tonic pitch is the swara Sa in the middle octave range of a performance. Automatic tonic identification is essential in South Indian Classical Music to perform computational melodic analysis based on data. The identification of the tonic in real time is often required to judge the quality of the singer or instrumentalist. In this era of a musical reality shows, an autonomous electronic system for tonic identification is very relevant in which the system accurately judges the competitor in terms of tonic perfection. In this proposed method, a tonic identification is performed by using the characteristics extracted from the pitch histogram through frequency ratio method. A mathematical model is proposed based on the parameters of the tonal histogram for tonic identification. In this context, a Tonic identification system also implemented in a Texas Instruments TMS320C6713 Digital signal processor.

Optimal design of zero-phase digital Riesz FIR fractional-order differentiator

This article introduces an optimal design of finite impulse response-type Riesz fractional-order digital differentiator (FODD) of orders p = 0.3, 0.5, and 0.75. A very little study on Riesz-based differentiator has been reported so far. Moreover, none of the published Riesz FODD-based literature has studied the optimal design of Riesz FODD, which is explored in this article. In the reported literature, the Riesz FODD is realized by adopting conventional mathematical approaches, which are not efficient for the Riesz FODD-type design problem where the nature of the search landscape is multidimensional, multimodal, non-uniform, and nonlinear. To solve this problem, the design parameters of the proposed Riesz FODDs are estimated by using three independent metaheuristic optimization algorithms called salp swarm algorithm (SSA), gases Brownian motion optimization (GBMO), and gravitational search algorithm (GSA). In SSA, the adaptive variation of the iteration-dependent parameters helps the search agents not only to avoid the suboptimal solutions, but also ensures the faster convergence to reach the near-global optimal solution compared to GSA- and GBMO-based design approaches. The maximum phase error (MPE) and maximum absolute magnitude error (MAME) of the proposed SSA-based Riesz FODD are as low as 3.7119E−014 degree and − 9.6824 dB, respectively, for p = 0.3; 3.1523E−014 degree and − 15.6443 dB, respectively, for p = 0.5; and 3.5780E−014 degree and − 18.7525 dB, respectively, for p = 0.75. In terms of MPE and MAME, the proposed SSA-based Riesz FODD significantly outperforms the GSA- and GBMO-based Riesz FODD designs. The proposed SSA-based Riesz FODD of order p = 0.5 is also implemented on the TMS320C6713 digital signal processor, and its precise zero-phase performance is tested on real electrocardiogram (ECG) signal. Moreover, the proposed Riesz FODD is utilized in the ECG QRS complex identification system to demonstrate its real-time application.

Digital Signal Processor (Tms320c6713) Based Abnormal Beat Detection from ECG Signals

In this work, arrhythmia detection and classification from ECG signals has been performed using a digital signal processor- TMS320C6713. Two of the predominant ECG arrhythmias- premature ventricular contraction (PVC) and atrial fibrillation (AF) have been addressed in this work. In order to distinguish the PVC and AF beats from normal ECG beats, algorithms based on the morphological characteristics of arrhythmias have been applied. The PVC and AF beats present in ECG signals have been classified using correlation-based algorithm, in which a PVC or AF beats are compared/correlated with a normal ECG beat. The correlation coefficient value for normal ECG beats for a particular ECG signal is above 0.9 (highly correlated) whereas for a PVC or AF beats its value is in the range of 0.09 to 0.3 (highly uncorrelated). Another algorithm, based on slope/amplitude, has been implemented for detecting the PVC beats from ECG signals. The slope/ amplitude-based algorithm detects the PVC beats with 98.94% accuracy as compared to 65.20% accuracy by correlation-based algorithm. Thus, slope/amplitude-based algorithm outperforms the correlation-based algorithm as two parameters -the slope of QRS complex and R wave amplitude- are considered for detecting the abnormal beats. This work presents a DSP processor-based system, ideal for use in real time applications, for detecting PVC and AF beats from ECG signals.

Secure Communication Based on Hyperchaotic Chen System with Time-Delay

An experimental secure communication method based on the Chen system with time-delay is being proposed in this paper. The Chen system with time-delay is an infinite-dimensional system having more than one positive Lyapunov exponent. The message to be transmitted is encrypted using an hyperchaotic signal generated by the Chen system with time-delay and multishift cipher function. This encryption makes difficult for an eavesdropper to reconstruct the attractor by using time-delay embedding techniques, return map reconstruction, or spectral analysis, consequently, improving the security. Simulations and experiments on TI TMS320C6713 Digital Signal Processor (DSP) show improved resilience against attack and the feasibility of the proposed scheme.

Differential current‐based fault protection with adaptive threshold for multiple PV‐based DC microgrid

A new differential current-based fast fault detection and accurate fault distance calculation is proposed for photovoltaic (PV)-based DC microgrid. A multiterminal direct current (MTDC) distribution network is studied as an adequate solution for present low-voltage utility grid scenario, where local distributed generators (DGs) are incorporated primarily by power electronics based DC-DC converters, DC-AC voltage-source converters (VSCs). PV and diesel generator (as auxiliary source) are considered for cascaded common DC bus, and AC utility bus integration is achieved by VSC unit for the proposed MTDC network. DC microgrid protection is quite significant research focus due to the absence of well-defined standards. Pole-to-pole, pole-to-ground, PV-side DC series and ground arc faults are basically considered as DC distribution network hazards. A discrete model differential current solution is considered to detect, classify and locate the faults by modified cumulative sum average approach. A comprehensive case study is presented with different DC loadings, to deliberate effectiveness of the proposed protection scheme in terms of percentage error and trip time ( Ts ). The result verification is conducted in MATLAB environment as well as TMS320C6713 digital signal processor- based test bench with the proposed multiple DGs based DC microgrid.

다채널 실시간 능동 소음제어 시스템을 이용한 정숙공간 성능개선

3차원 잡음환경에서 정숙공간은 현실적으로 매우 중요한 문제이다. 본 논문은 3차원 잡음 환경에서 정숙 공간의 성능을 크기와 소음제거 면에서 향상시키는 다채널 실시간 능동소음 제어시스템의 개발과 구현을 다루고 있다. 제안된 능동소음제어 시스템은 delay-compensated Filtered-X Least Mean Square (FXLMS) 알고리즘을 적용한다. 이와 같은 시스템의 실시간 적용을 위해서 TMS320C6713 DSP 프로세서 기반으로 설계되었다. 제안된 실시간 다채널 능동소음제어기의 성능평가는 100 ~ 500 Hz 범위의 다양한 잡음 환경에서 잡음제거를 수행하고, 정숙공간에서 음압레벨(Sound Pressure Level, SPL)측정하여 평가하였다. 실험결과는 정숙공간의 크기는 만족스러우며 최대 24 dB의 소음 감쇄가 성공적으로 생성된 것을 보여준다. Generation of a quiet zone in noisy environment is undoubtedly of considerable realistic significance. This paper describes development and implementation of a multichannel real-time active noise control (ANC) system for 3 dimensional noisy environment to enhance the quiet zone performance in terms of size and noise cancellation gain. The proposed ANC system employes a multichannel delay-compensated filtered-X least mean square (FXLMS) algorithm; its real-time implementation is designed in TMS320C6713 digital signal processor (DSP) board. The system is evaluated for cancelling various tonal frequency noises in the range from 100 to 500 Hz, and the performance is then illustrated by measuring the quiet zone in terms of sound pressure level (SPL) attenuation. Experiment results show that a quiet zone of quiet with satisfactory size and maximum 24 dB noise attenuation is successfully generated.

Secure communication based on spatiotemporal chaos**Project supported by the National Natural Science Foundation of China (Grant No. 61172070) and the Funds from the Science and Technology Innovation Team of Shaanxi Province, China (Grant No. 2013CKT-04).

In this paper, we propose a novel approach to secure communication based on spatiotemporal chaos. At the transmitter end, the state variables of the coupled map lattice system are divided into two groups: one is used as the key to encrypt the plaintext in the N-shift encryption function, and the other is used to mix with the output of the N-shift function to further confuse the information to transmit. At the receiver end, the receiver lattices are driven by the received signal to synchronize with the transmitter lattices and an inverse procedure of the encoding is conducted to decode the information. Numerical simulation and experiment based on the TI TMS320C6713 Digital Signal Processor (DSP) show the feasibility and the validity of the proposed scheme.

English

This paper suggests Digital Signal processor (DSP) based speech recognition system with improved performance in terms of recognition accuracies and computational cost. The comprehensive surrey of various approaches of feature extraction like Mel filter banks with Mel Frequency Cepstrum Coefficients (MFCC). This paper describes an approach of isolated speech recognition by Digital Signal Processor TMS320C6713 using Mel scale Frequency Cepstral Coefficients and Euclidean distance. Several features are extracted from speech signal of spoken words. An experiments database of total five speakers, speaking 5-10 words each is collected under acoustically controlled room is taken. MFCC are extracted from speech signal of spoken words. To compare inter speaking differences Euclidean distance is used

GMSK NEURAL NETWORK BASED DEMODULATOR

In this paper, the pattern recognition characteristics of the Artificial Neural Net­ works are used to realise a real demodulator for Gaussian Minimum Shift­Keying signals, used in the GSM telecommunications. The demodulator utilises the Learning Vector Quantisation (LVQ) neural network. It offers both greater efficiency in demodulating and less sensitivity to noise. In order to solve the problem regarding input signal synchronisation, a pre­processing phase is organised. The demodulator prototype has been realised by implementing the pre­processing phase and the LVQ neural network on TMS320C30 Digital Signal Processor. The demodulator has been tested according to the European Telecommunication Standard Institute Recommendations.

Compensation of Reconstruction Filter Effect in Digital Signal Processing System

This paper proposes the reduction effect of reconstruction filter for digital signal processing system. It is well known that the reconstruction filter limits the bandwidth of output signal processing and the output signal is staircase form or has high frequency components. For effect reduction we use the nonrecursive system which corresponds with the inverse system function of the reconstruction filter. The initial step starts with the analog system function of the reconstruction filter and is converted to a discrete-time system using the approximation of derivative technique and inverse system. This inverse discrete-time system function is a nonrecursive system to compensate the reduction effect of the reconstruction filter implemented by using the software. For hardware experiments, we use TMS320C31 digital signal processor, D/A, PIC-32 microcontroller, PWM analog output. The experimental results of the proposed principle show that it can be used to compensate the bandwidth and reduce the total harmonic distortion (THD) of high frequency signal. In addition, this experiment shows that the nonrecursive system for compensation uses only first-order system and it does not utilizes any more processor. Furthermore, it is able to increase the performance. The applications are such as digital filtering, digital control and audio processing. They can be done with high accuracy using the proposed principle.

A New Real-Time Fast Discrete S-Transform for Cross-Differential Protection of Shunt-Compensated Power Systems

This paper presents a cross-differential protection scheme for power transmission systems inclusive of a STATCOM. The measurement of the energy of the prominent frequency components of the current signals is done using a computationally fast version of the discrete S Transform suitable for power system signal analysis. The energy thus obtained is used for cross-differential purposes. The practical implementation of the new fast discrete S-transform is performed on the TMS320C6713 digital signal processor for verification of real-time operation of the relaying scheme. The computational load of the processor to perform the transform in online mode is reduced by a cross-differential check using a cumulative difference technique. The results obtained from the extensive experimentations show the feasibility and speed of the new approach.

A LabVIEW-Based GPS Receiver Development and Testing Platform with DSP Peripherals: Case study with C6713 DSK

The modernization of Global Positioning Systems (GPS) and the availability of more complex signals and modulation schemes boost the development of civil and military applications while the accuracy and coverage of receivers continually improve. Recently, software defined receiver solutions gained attention for flexible multimode operations. For them, developers address algorithmic and hardware accelerators or their hybrids for fast prototyping and testing high performance receivers for various conditions. This paper presents a new fast prototyping concept exploiting digital signal processor (DSP) peripherals and the benefits of the host environment using the National Instruments (NI) LabVIEW platform. With a reasonable distribution of tasks between the host hardware and reconfigurable peripherals, a higher performance is achieved. As a case study, in this paper the Texas Instruments (TI) TMS320C6713 DSP is used along with a Real Time Data Exchange (RTDX) communication link to compare with similar Simulink-based solutions. The proposed testbed GPS signal is created using the NI PXI signal generator and the NI GPS Simulation Toolkit.

DSP Implementation of Lattice Vector Indexing for Image Compression

Image-related interactions are forming an increasingly large part of modern communications, bringing the need for efficient and effective compression. Image compression is important for effective storage and transmission of images. Image processing applications are increasingly being done on embedded systems because image processing involves high computation and data requirements. This paper work describes the implementation of indexing of vectors quantized using lattice structure on TMS320C6713 Digital Signal Processor board. In this work for quantization of vectors D 4 lattice structure is selected. The proposed indexing technique is based on direct assignment of indices to the vectors. Generation of the codebook and the indexing of leader are not required in this method . The code is written in C in Code Composer Studio (CCS) in order to program the DSP processor. With the help of profile statistic available in CCS, statistical analysis is also carried out.

Design and Implementation of an Efficient Software Communications Architecture Core Framework for a Digital Signal Processors Platform

Problem statement: The Software Communications Architecture (SCA) was developed to improve software reuse and interoperability in Software Defined Radios (SDR). There had been performance concerns since its conception. Arguably, the majority of the problems and inefficiencies associated with the SCA can be attributed to the assumption of modular distributed platforms relying on General Purpose Processors (GPPs) to perform all signal processing. Approach: Significant improvements in cost and power consumption can be obtained by utilizing specialized and more efficient platforms. Digital Signal Processors (DSPs) present such a platform and have been widely used in the communications industry. Improvements in development tools and middleware technology opened the possibility of fully integrating DSPs into the SCA. This approach takes advantage of the exceptional power, cost and performance characteristics of DSPs, while still enjoying the flexibility and portability of the SCA. Results: This study presents the design and implementation of an SCA Core Framework (CF) for a TI TMS320C6416 DSP. The framework is deployed on a C6416 Device Cycle Accurate Simulator and TI C6416 Development board. The SCA CF is implemented by leveraging OSSIE, an open-source implementation of the SCA, to support the DSP platform. OIS’s ORBExpress DSP and DSP/BIOS are used as the middleware and operating system, respectively. A sample waveform was developed to demonstrate the framework’s functionality. Benchmark results for the framework and sample applications are provided. Conclusion: Benchmark results show that, using OIS ORBExpress DSP ORB middleware has an impact for decreasing the Software Memory Footprint and increasing the System Performance compared with PrismTech's e*ORB middleware.

Simulation and Spectral Analysis of the Scrambler for 56Kbps Modem

Scrambler is a device that performs one-to-one mapping between input data bits and channel codes. It is used in synchronous data communication systems to retrieve timing information from the received data i.e. to aid synchronization between two modems. Present paper deals with the computer-aided simulation and spectral analysis of the scrambler to be used in 56Kbps voice-band modem. Matlab has been used for simulation and pre-spectral analysis including power spectral density, cross-correlation and auto-correlation. Implementation of scrambler has been done on Texas Instrument's TMS320C50 digital signal processor (DSP) and post- spectral analysis has been performed using Signalogic DSP software. Simulated and practical results have been found identical, which ensures the successful implementation of scrambler.

Real-time H.264/AVC baseline decoder implementation on TMS320C6416

The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288)

A DSP based channel selection algorithm for adaptive transmission in indoor power line

Unpredictable noise and transfer function in power line channel make it a hostile environment for communication. The paper presents an algorithm which is implemented on a TMS320C6713 Digital Signal Processor (DSP) to select the best channel suitable for transmission. A design of a suitable hardware where the system can be used is also presented.

DSP-based control of a high frequency three cell flying capacitor inverter

The design, instrumentation and early operation results of a digitally controlled voltage source inverter (VSI) are described. This inverter has been structured from a three cell flying capacitor inverter (TCFCI). Two different inverter control modes – open-loop and closed-loop – are applied by a digital system based on a Texas Instrument TMS320C6713 digital signal processor (DSP) board. The VSI is able to generate AC voltage signals up to 120 V amplitudes at a maximal 6 A current, from ∼9 kHz to ∼60 kHz in ∼900 Hz steps in both controls by varying the signal period through the square-wave command strategy. The multi-cell structure of the inverter provides an output frequency nearly three times that of the TCFCI semiconductor commutation. The power output of the TCFCI can drive a high frequency step-up transformer which, in turn, is associated with a cylindrical reactor where dielectric barrier discharges (DBD) are conducted.

비례적분제어기와 feedforward 외란상쇄 관측기의 비교분석

이 논문은 피드포워드 왜란상쇄 관측기를 이용하여 유도전동기의 강인한 제어를 얻을 수 있었다. 전통적인 비례적분 제어기의 속도응답 특징은 부하 토크 요소의 변이에 영향을 받는다. 제안한 시스템에서 속도제어 특성은 부하토크 외란에 영향을 받지 않는 피드포워드 제어를 사용하였다. 벡터제어를 위한 높은 속도의 계산과 처리를 위해 TMS320C31 디지털 프로세서를 사용하였다. 제안한 제어 방법의 타당성을 입증하기 위해 시뮬레이션과 실험을 통해 확인하였다. This paper designed a robust control of an induction motor using a disturbance cancellation observer of a feedforward control. The speed response of conventional PI controller characteristic is affected by variations of load torque disturbance. In the proposed system, the speed control characteristic used a feedforward control which does not undergo the influence of the load torque disturbance. High speed calculation and processing for vector control is carried out by TMS320C31 digital signal processor. Validity of the proposed control method is verified through simulation and experimental result.