Digital Signal Processing Unit Research Articles

A coherent MMW-ROF link employing mixed modulations and photonic down-conversion

We propose and experimentally demonstrate a coherent millimeter wave radio-over-fiber (MMW-ROF) link employing mixed modulations with a simple digital signal processing (DSP) unit. At the transmitter, a light wave is intensity and phase-modulated by two microwave vector signals in a dual-parallel Mach–Zehnder modulator (DP-MZM). At the receiver, by using a 3-line optical frequency comb (OFC) signal as the optical local oscillator (OLO), the microwave vector signals can be photonically down-converted to intermediate frequency (IF) signals. Then, instead of a complex digital phase-locked loop (DPLL), simple algorithms are used to remove the laser phase fluctuation between two free-running lasers and do the demodulations. In the 25 km fiber transmission experiments, we successfully down-convert two 50 Msymbol/s 16-quadrature amplitude modulation (16-QAM) signals at 25 GHz and 24 GHz to intermediate frequencies of 2 GHz and 1 GHz. The transmission performance of the proposed link in terms of error vector magnitudes (EVMs) are also investigated. The results show that when the receiver optical power is -20 dBm, the measured EVMs are still less than 12.5% which satisfies the 3rd Generation Partnership Project (3GPP) standard.

Method of increasing the range resolution of radio pulse sensors of short-range radar systems

The description of a new method for increasing the resolution of radio pulse sensors (RPS) designed for short- range radar systems (SRRS) for detecting and measuring motion parameters of location objects is presented. The essence of the method is that the controlled area of space with the targets located in it is periodically irradiated with probing radio pulses, and during their radiation, radio pulses reflected from the targets are simultaneously received and divided into two quadrature channels. Next, they are mixed with probing radio pulses, and the time-overlapping parts of these radio pulses are converted into the region of low Doppler frequencies in the form of two quadrature video pulses. Then, the quadrature video pulses received in these channels are sampled by amplitude, stored at multiple points in time and digitally processed according to the proposed algorithm. The method is implemented in the RPS made on the basis of a horn-lens antenna, a Doppler receiving and transmitting module with quadrature outputs of converted signals, a synchronization and pulse generation unit, as well as a digital signal processing unit. The RPS can be used in onboard (for example, automotive) SRRS designed to detect moving targets, measure the distance to them, as well as determine the speed and direction of movement. The results of experimental studies have been obtained on the example of the 8-mm autodyne RPS made on the basis of the oscillator on a planar Gann-diode.

Sparse Volterra Equalizer to Mitigate the Nonlinear Distortion in High Power Budget IM-DD OFDM PON

To improve the power budget for intensity-modulation direct-detection (IM-DD) orthogonal frequency division multiplexing passive optical network (OFDM PON), a high power budget downstream scheme by using the Volterra equalizer in digital signal processing (DSP) processing is proposed in this paper. When the launch power is increased, the subcarrier-to-subcarrier beating interference (SSBI) and other nonlinear distortion are well mitigated by the Volterra equalizer. Moreover, to reduce the complexity of receiver DSP unit, the sparse Volterra equalizer is obtained through optimizing full Volterra equalizer employing orthogonal search method. Simulation and experiment results are presented to evaluate the transmission performance and analyze the distribution of taps of Volterra equalizer under different respects. The results show that the number of tap coefficient of sparse Volterra equalizer is reduced by 60% compared with that of conventional second-order full Volterra equalizer.

Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection

Semiconductor technologies have gained wide-spread attention across industries due to its use in varied digital signal processing units, healthcare-devices, industrial communication, science and technologies, entertainment, smart devices etc. However, high design-complexities, untrusted foundries, third-party processors etc., have raised the concern of intrusion, particularly Hardware Trojans. Hardware Trojan, a specifically designed micro-intruder that can cause data breaches, system malfunctions etc. And hence may result disastrous consequences. To alleviate such problems, though different methods have been suggested for Trojan detection; however, pre-manufacturing methods can't guarantee Trojan-free design due to non-trusted Foundries and Third-party IPs. Similarly, post-manufacturing methods like side channel analysis or gate -level netlist are limited due to highly complex design, large structure and unavailability of universal golden design structures. Considering it as motivation, this paper proposes a robust register transfer logic (RTL) analysis assisted multi-parameter-based machine learning-driven Hardware Trojan detection system. We applied delay, power consumption and resource utilization profiles to perform Trojan detection over AES-256 circuits. Aforesaid features were extracted using VIVADO tool, which were further employed for resampling process using SMOTE, SMOTE-ENN, SMOTE-Borderline algorithms. Here, the use of resampling intended to alleviate data-imbalance or skewness. Moreover, it helped retaining sufficiently large features for machine learning based training. The resampled features were processed for feature selection using Significant Predictor Test, Cross-Correlation Test and Principal Component Analysis (PCA), distinctly. The selected features were trained using a novel heterogenous ensemble learning model encompassing a total of 11 base-classifiers belonging to Naïve Bayes, Neuro-computing, Decision Tree, Random Forest, Extra Tree classifier and Bagging-AdaBoost algorithms. Applying the maximum voting ensemble, the proposed model performed path-level Trojan detection, where the simulated results affirmed accuracy, F-Measure and Area Under Curve (AUC) of almost 100%, which is higher than any known approaches towards Hardware Trojan detection.

Совершенствование формы плоских антенных решеток для повышения точности радиолокации со сверхразрешением

A promising way to increase the bandwidth and noise immunity of modern wireless information transmission systems is the use of antenna arrays equipped with a digital signal processing unit, which include MIMO systems (Multiple Input Multiple Output), as well as adaptive (smart) antennas. The main advantage of this approach is the antenna’s spacing, which makes it possible to assess the angular coordinates of radio signals with further developing 
 a radiation pattern. Gaps in studying the influence of the lattice geometry together with various kinds of antenna elements are known to be one of the factors of inaccuracy of such systems. The work is aimed at obtaining the shape 
 of a planar antenna array with a higher direction finding accuracy. There is described an algorithm for calculating such an arrangement of antenna elements of flat antenna arrays, in which the standard deviation of the estimates of the angular coordinates of one and two radio signal sources is reduced. The proposed approach is based on the analysis 
 of the influence of antenna location on the variance of estimates described by the lower boundary of Kramer-Rao. This value shows the influence of the location of antenna elements on the accuracy of estimating the direction of arrival of a joint assessment with two signal sources. It has been shown that the accuracy of the direction-of-arrival non-joint estimation is determined as the sum of squared differences between all coordinates of omnidirectional elements along the X- and Y-axis if one signal arrives. If two signals arrive, the accuracy of the direction-of-arrival joint estimation depends on the sum of cosines having the argument with the difference between sensor coordinates and signals radius-vectors. The optimal location of the antenna elements using the obtained expressions can be calculated very easily to reduce the direction-finding errors near particular sectors. In order to confirm the proposed method, there were studied the antenna arrays built after minimizing the boundary of Kramer-Rao, where the target functions are the new expressions. It is found out that the new shapes of antenna arrays based on the analytical expressions have better direction-of-arrival accuracy in comparison with the circular ones.

A Procedure for Precise Determination and Compensation of Lead-Wire Resistance of a Two-Wire Resistance Temperature Detector.

A procedure for the precise determination and compensation of the lead-wire resistance of a resistance transducer is presented. The proposed technique is suitable for a two-wire resistance transducer, especially the resistance temperature detector (RTD). The proposed procedure provides a technique to compensate for the lead-wire resistance using a three-level pulse signal to excite the RTD via the long lead wire. In addition, the variation in the lead-wire resistance disturbed by the change in the ambient temperature can also be compensated by using the proposed technique. The determination of the lead-wire resistance from the proposed procedure requires a simple computation method performed by a digital signal processing unit. Therefore, the calculation of the RTD resistance and the lead-wire resistance can be achieved without the requirement of a high-speed digital signal processing unit. The proposed procedure is implemented on two platforms to confirm its effectiveness: the LabVIEW computer program and the microcontroller board. Experimental results show that the RTD resistance was accurately acquired, where the measured temperature varied from 0 °C to 300 °C and the lead-wire resistance varied from 0.2 Ω to 20 Ω, corresponding to the length of the 26 American wire gauge (AWG) lead wire from 1.5 m to 150 m. The average power dissipation to the RTD was very low and the self-heating of the RTD was minimized. The measurement error of the RTD resistance observed for pt100 was within ±0.98 Ω or ±0.27 °C when the lead wire of 30 m was placed in an environment with the ambient temperature varying from 30 °C to 70 °C. It is evident that the proposed procedure provided a performance that agreed with the theoretical expectation.

Implementation of the High Speed PLL

the most multipurpose application of the phase locked loops (PLL) is for clock generation and clockrecovery in microprocessor, networking, communication systems, and digital circuit and frequency synthesizers.Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks inhighperformance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter (deviation) reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with fasterlocking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time.PLL is a mixed signal circuit as itsarchitecture involves both digital and analog signalprocessing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in EDA TANNER Design Environment.Here a current starved ring oscillator has been considered for its superior performance in form ofits low chip area, low power consumption and wide tunable frequency range. Thesimulation results ofPLL are reported in this work. It is found that the designed PLL consumes 11.68mW power froma 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) isthe heart of the PLL, so the optimization of the VCO circuit is also carried out using the optimization technique. The results of the VCO designed are shown. Keyword: PLL, VCO, GDPK 900, Charge pump (CP).

Минимизация нижней границы Крамера-Рао для построения антенных решеток с направленными излучателями для повышения точности оценок угловых координат радиосигналов

The use of antenna arrays equipped with digital signal processing units is a promising way to increase the throughput, noise immunity of modern wireless information transmission systems. The spatial diversity of the antenna is the main advantage of this approach which makes it possible to estimate the spatial coordinates of radio signals with subsequent beamforming. It is well known that the insufficient knowledge of the influence of the array geometry together with various types of antenna elements (such as a dipole, a patch, etc.) may be a cause reducing the accuracy of such systems. The article describes an approach aiming at reducing direction-of-arrival estimation errors of radio signal sources by means of optimal antenna array geometries. In particular, the Cramer-Rao lower bound is used for the task. The quantity sets a limit below which one or another algorithm for estimating the spatial coordinates of signal sources cannot descend for a particular geometry of the antenna array. The expressions based on the Cramer-Rao lower bound are derived which describes the dependence of the variance of direction-of-arrival estimation errors on the location of the array elements in the Cartesian coordinate system, i.e. along the x, y, z axes. In addition, the function of the radiation patterns of individual antennas is taken into account in the obtained formulas. Additionally it is considered that the antenna elements are directional. Therefore, the proposed technique is aimed at reducing the variance of direction-of-arrival estimation errors of statistical algorithms with superresolution by minimizing the obtained new formulas. As a result, the optimal locations of antenna elements along the x, y, z axes are calculated. In the paper, new geometries of antenna arrays have been obtained according to the proposed approach. In particular, two- and six-element arrays are researched, which are compared with equally spaced cylindrical ones. Graphs of the error variance of the Cramer-Rao boundary are presented, as well as a statistical study of the MUSIC method. It is shown that the magnitude of errors is reduced by new antenna arrays in all the researching scenarios. Thus the antenna arrays geometries obtained in this paper allow improving the accuracy of algorithms for estimating the angular coordinates of radio signals with superresolution.

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System.

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were designed to minimise power and area consumption without sacrificing throughput. All designs were validated in a Field Programmable Gate Array (FPGA) and compared against unrestricted CPU-MATLAB implementations. Furthermore, a (2,2,2,2) MLP with back propagation was implemented and tested in a FPGA showing a total hardware utilisation of just 3782 LUTs, and no DSP or BRAMs. The MLP was also built in a Application Specific Integrated Circuit (ASIC) using a 130 nm technology by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Skywater 130A</i> . The results show that the area occupation was just 0.12 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumed just 100 mW at 100 MHz input stimulus.

Design and performance evaluation of a multi-axis thin-film sensor for milling process measurement

A multi-axis sensor made of flexible, light, and sensitive PVDF (polyvinylidene fluoride) thin film is designed and fabricated for cutting force measurement in milling process. The single-layer PVDF thin film is constructed with six electrodes in a certain pattern, which has two electrodes in each pair to measure the signals due to bending moment as well as torque moment on the cutter in the process of milling. All the detected voltage signals will be calibrated by the digital signal processing unit and transmitted to the remote receiver via wireless communication. A cutting-force model is established in association with the measurement scheme that can compute the feed force, transverse force, and tangential force via the collected voltage signals from the electrodes. In experiment, the PVDF sensor is directly attached to the cutter, and the commercial dynamometer is implemented under the workpiece for synchronous measurement and comparison. As a result, the developed thin-film sensor associated with the sensing circuitry and wireless communication device as well as the cutting force model can effectively measure the important cutting force with satisfactory accuracy.

Prototype design of readout electronics for Zero Degree Calorimeter in the HIRFL-CSR external-target experiment

Located at the center of the end of the CSR External-target Experiment (CEE), the Zero Degree Calorimeter (ZDC) is designed to rebuild the centrality and reaction plane of the nuclear-nuclear collision. To meet the target of ZDC to detect the energy distribution of colliding particles, a high-performance readout system prototype, which implements a Gaussian shaping algorithm, has been designed. The system consists of 4 channels; each channel mainly includes an I-V conversion circuit, a slow forming circuit, a threshold trigger circuit, and a digital signal processing unit based on a field-programmable gate array (FPGA).Performance studies indicate that the noise of each channel is less than 0.8 mV and the nonlinearity is better than 0.6%. Tests with a LED driver source indicate that the Gaussian shaping algorithm can improve the photon energy resolution from 7.481% to 6.196%. Tests with cosmic rays also produced expected results.

Optical-Magnetometry-Based Current Source

We present a current monitoring system based on optical magnetometry, which is able to discriminate true current variations from environmental effects at room temperature. The system consists of a dedicated thermally stable magnetic field confining coil and an array of four optically pumped magnetometers arranged in a two-dimensional gradiometer configuration. These magnetometers monitor magnetic field variations inside the coil, which correlate to the variations of the driving current of the coil. The system uses a digital signal-processing unit to extract and record in real time the magnetic field values measured by the magnetometers, which allows a real time monitoring of the current. The system's coil, which is made out of printed circuit boards, can easily be changed to adapt the current-to-field conversion. Thus, we can expand the applicability of this system to a wide range of currents. By using this system to actively feedback control a current source we stabilized a current of 20 mA on a level better than $5 \times 10^{-9}$.

Fast Binary Counters and Compressors Generated by Sorting Network

The summation of multiple operands in parallel forms part of the critical path in various digital signal processing units. To speedup the summation, high compression ratio counters and compressors are necessary. In this article, we present a novel method of fast saturated binary counters and exact/approximate (4:2) compressors based on the sorting network. The inputs of the counter are asymmetrically divided into two groups and fed into sorting networks to generate reordered sequences, which can be solely represented by one-hot code sequences. Between the reordered sequence and the one-hot code sequence, three special Boolean equations are established, which can significantly simplify the output Boolean expressions of the counter. Using the above method, we construct and further optimize the (7,3) counter that can perform 27.0%, 26.2%, and 52.0% better in maximum than other designs in delay, area-delay product, and power-delay product, respectively. Similarly, the (15,4) counter is constructed, and it achieves approximately 35.3% shorter delay, while it significantly consumes less power and area. The constructed (31,5) counter has approximately 26.7% higher performance with the area increasing instead. When the counters are embedded in a 16×16 bit multiplier, the performance of the multiplier in area delay product and power delay product is 31.8% and 32.1% higher than that embedded in other counter designs, respectively. Besides, we also construct exact/approximate (4:2) compressors based on sorting network, and they are 10.2%-37.4% better in the area-delay product and 22.3%-48.0% better in power-delay product when they are embedded in an 8×8 bit approximate multiplier.

Performance Analysis of a Full-Duplex TWDM-PON Using OFDM Modulation with Red LED Visible Light Communication System

Today’s access networks are in high demand to fulfill the high bandwidth requirement because of extensive improvement in high transmission rate applications for cloud computing, big data analytics, and other next-generation 5G smart applications. In this work, the symmetrical and bidirectional time and wavelength division multiplexing-passive optical network (TWDM-PON) system is proposed and demonstrated. Orthogonal frequency division multiplexing (OFDM) with 4-level quadrature amplitude modulation is used for downstream and upstream transmission. Also, 625 nm red light-emitting diode is utilized for visible light communication (VLC) using a wireless link to encourage the economic high transmission rate fiber/VLC optical network. The TWDM-PON employing OFDM with the VLC system has been analysed for downstream and upstream channels for variable fiber-wireless link range. Additionally, the impact of a high transmission rate and usage of digital signal processing (DSP) unit to reduce losses due to fiber nonlinearity effects in the proposed link has been investigated. The results show that the maximum faithful wireless and wired range for the proposed system is 140 m and 60 km respectively at 20 Gbps to attain the minimum 3.8 × 10−3 BER. The decrease in error vector magnitude (EVM%) by almost 52% with the use of DSP in the proposed system provides a high transmission rate of 200 Gbps in the proposed link. Further, comparative performance of the proposed system with previous latest works in literature reveals a superior performance of the proposed link. The proposed TWDM-PON system provides a next-generation access network from rural areas to urban areas.

Development of a Wide Dynamic Range Neutron Flux Measurement Instrument Having Fast Time Response for Fusion Experiments

A wide-range neutron flux measurement instrument is developed herein for monitoring the total neutron emission rate and yield of the Large Helical Device (LHD) during deuterium experiments implemented from March 2017 in the National Institute for Fusion Science (NIFS), Japan. The instrument is designed for and installed on the Neutron Flux Monitoring (NFM) system, which measures the counting rate using a 235U Fission Chamber. By combining the pulse counting and Campbell methods, the Digital Signal Processing Unit (DSPU) realized a wide dynamic range of over six orders of magnitude from 1 × 103 counts/s (cps) to 5 × 109 cps. This study explains and discusses how the instrument is developed, including topics from the predevelopment activities to the verification test at the Kyoto University Critical Assembly (KUCA). Experimental results in the LHD using the finished products suggest that the NFM system works well during deuterium experiments.

Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

AbstractNext-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Design and Integrate Real Time Clock and Temperature Digital Signal Processing with ARM System

The integrated circuit had been developed rapidly from microprocessor to microcontroller and System-on-Chip (SoC) just happen within a few decade. The development is continuing as the demand for the functionality increase. The Real Time Clock (RTC) is one of the peripherals most widely used inside the microcontroller. Besides, when Moore’s law is still applied, the number of transistor will increase, so does the temperature. Thus, the temperature digital signal processing (TDSP) unit had become an important peripheral to monitor the system-on-chip temperature. In this paper, these two Intellectual Property which are RTC and TDSP are designed and integrated into ARM system. The system architecture and implementation strategies are discussed. The results were run and simulated in the Synopsys software.

A detailed introduction of different beamforming techniques used in 5G

SummaryThe arrival of high‐speed internet facility such as the mmWave system or more commonly known as 5G wireless network is a prime impetus that is expected to be the driver for radical transformation in current communication methods. Apart from the numerous applications, an area where 5G is expected to be a game‐changer is the vehicle‐to‐everything or V2X network. This technology uses a road side unit (RSU) which provides wireless connectivity to vehicles, pedestrians, and so on, which may be either stationary or mobile so that their exact location can be known in real time. Researchers have demonstrated experimentally that 4G connectivity with such RSUs can provide a reliable low latency network for certain applications. For instance, for near‐perfect localization of each connected objects on the map, there is a need to stream GPS data, process semantic information from videos continually using computer vision. While these are simply for locating vehicles in real time so that road accident can be prevented. They are also the host of other features such as entertainment, health monitors, and mobile office that can be integrated inside a moving vehicle. To address the issues massive multi‐input multi‐output (MIMO), communication can be realized by using hybrid transceivers which uses a setup consisting of high‐dimensional analog phase shifters and power amplifier with dimensional digital signal processing units having low power. It is therefore vital to choose an apt beamforming design that will run on low energy. A comparison of different varieties of beamforming methodologies for determining the most efficient massive MIMO network is carried out here.

A facile approach to design truncated multiplier based on HSCG-SCG CSLA adder

Applications such as audio processing, signal processing, SDR and such will work with elite efficiency in recent decades of technology development, in the context of sign preparation and image handling, and are extremely convenient as far as the area is concerned. There may be more signal noises and inconsistencies in digital signal processing units which use all categories of gadgets. In contrast, these applications consume greater areas in practical deployment in VLSI due to the arithmetic operation of the Adders and Multiplier design. Here, the proposed advanced method intends to design a novel outlook of FIR filter by replacing adders and multipliers to the proposed signed and unsigned Truncation Multiplier and HSCG-SCG adders. In this approximate partial reduction of products, the structure of truncation multiplier will have a number of the adders. This proposed work also attempts to replace these adders to HSCG-SCG method. This proposed design will reduce the number of logic gates in arithmetic operation of multiplication, addition and also proves efficient in signed and unsigned methods of signal processing applications.