Fast Binary Counters and Compressors Generated by Sorting Network

Abstract

The summation of multiple operands in parallel forms part of the critical path in various digital signal processing units. To speedup the summation, high compression ratio counters and compressors are necessary. In this article, we present a novel method of fast saturated binary counters and exact/approximate (4:2) compressors based on the sorting network. The inputs of the counter are asymmetrically divided into two groups and fed into sorting networks to generate reordered sequences, which can be solely represented by one-hot code sequences. Between the reordered sequence and the one-hot code sequence, three special Boolean equations are established, which can significantly simplify the output Boolean expressions of the counter. Using the above method, we construct and further optimize the (7,3) counter that can perform 27.0%, 26.2%, and 52.0% better in maximum than other designs in delay, area-delay product, and power-delay product, respectively. Similarly, the (15,4) counter is constructed, and it achieves approximately 35.3% shorter delay, while it significantly consumes less power and area. The constructed (31,5) counter has approximately 26.7% higher performance with the area increasing instead. When the counters are embedded in a 16×16 bit multiplier, the performance of the multiplier in area delay product and power delay product is 31.8% and 32.1% higher than that embedded in other counter designs, respectively. Besides, we also construct exact/approximate (4:2) compressors based on sorting network, and they are 10.2%-37.4% better in the area-delay product and 22.3%-48.0% better in power-delay product when they are embedded in an 8×8 bit approximate multiplier.