Digital Signal Processor Implementation Research Articles

DSP Implementation of the Particle Swarm and Genetic Algorithms for Real-Time Design of Thinned Array Antennas

Efficient implementation of sophisticated algorithms on digital signal processing (DSP) chips is a key issue in the implementation of software-defined radios. Here, focusing on beamforming and using the average calculation time and hardware usage as the two indicators of efficiency, a performance comparison between two versions of binary particle swarm optimization (PSO) and genetic algorithm, as the two popular evolutionary techniques, is presented. Using our proposed multirun strategy in DSP platforms, we show that modified PSO results in a reduction by 52% and 67% in the hardware utilization and calculation time as compared to genetic algorithm and binary PSO, respectively.

Digital automatic voltage regulator for synchronous generator considering sensor failure

SUMMARYIn this paper, digital signal processor (DSP) based automatic voltage regulator (AVR) for synchronous generator is proposed. The control performance of AVR is guaranteed to be more reliable by the application of measurement validation method based on Polynomial Chaos Theory. Analysis and development of the proposed regulator is done by both computer simulations and DSP implementation. A hardware platform of the AVR, which consists of two DSPs as the microprocessor is set up, one DSP is used for calculation of the sampled data and sensor validation, the other is used for control algorithm application. Several other methods have also been adopted in the configuration of the hardware for a better dynamic performance. Steady state and dynamic control performance of the regulator are investigated on different working conditions (such as voltage establishment, load connection, and sensor failure). Experimental results show good consistency to the theoretical analysis. Copyright © 2011 John Wiley & Sons, Ltd.

Half-Band Filter Design Based on MATLAB and FPGA

Half-band filter is a linear phase FIR filter, which is symmetric-even and odd .Because the coefficient of half-band filter is symmetrical and nearly half of the coefficient are zero, it make the filters reduce the number of multiplication operations by almost 3 / 4, and the number of addition operations by nearly half . The memory used to store filter coefficients are also reduced by half, so it make the implementation of efficient real-time digital signal processing more conducive. The half-band filter has many characteristics: for instance, simple structure, easy to implement and excellent performance, it is widely used in multi-rate system. This paper first describes the principle of half-band FIR filter, the character and method for implementation, then puts forward the design and simulation process which is based on MATLAB and Xilinx's half-band filter, and at last analyses the result.

Implementation of proportional integral (PI) controlled DSP based cost effective inverter fed speed control of induction motor drive with VisSim/ embedded controls and developer (ECD)

Real-time implementation of PI controller based cost effective inverter fed speed control of induction motor drive using high performance TMS320F2812 DSP with VisSim/ embedded controls and developer (ECD) is presented in this paper. The four switch three-phase inverter (FSTPI) fed drive system consists of a power circuit having an insulated gate bipolar junction transistor (IGBT) based bridge inverter module feeding a 5 hp three-phase squirrel cage induction motor and control circuits that comprises of digital signal processor (DSP), processor board, driver circuit, sensor (for sensing speed signals), interfacing circuits and PC with VisSim/ECD software. The PI controller block and PWM generation block of this drive system are designed using VisSim/ECD to control the speed of induction motor in closed loop. Observations are made by changing speed of motor at different loads. Results obtained from this experimental work are satisfactory and shown using GUI of VisSim /ECD software and digital storage oscilloscope. Key words: Four switch three-phase inverter (FSTPI), digital signal processor (DSP), proportional integral (PI), Sinusoidal pulse width modulation (SPWM) and VisSim/ embedded controls and developer (ECD).

Experimental architecture of a DSP based signal generation for PWM inverter

AbstractThis article presents the analysis and design of an experimental study on the implementation of digital signal processor (DSP) controlled single‐phase pulse width modulation (PWM) inverter based on Simulink and Real Time Workshop in Matlab. Each stage of PWM signal generation using DSP is comprehensively presented to ease the design and analysis of complicated control algorithms in DSP based solutions. The article also enhances knowledge more about experimental studies in the laboratory. The performance of the DSP based PWM inverter design is analyzed through simulation studies under various switching frequencies and the theoretical considerations are successfully validated with experimental prototype based on TMS320F2812 DSP. © 2009 Wiley Periodicals, Inc. Comput Appl Eng Educ 19: 561–571, 2011

Digital Signal Processor Implementation of Isolated Reduced-rating Voltage Source Converter Using a Zig-zag Transformer for Three-phase Four-wire Distribution Static Compensator

The proposed distribution static compensator is used to compensate the reactive power for power factor correction or voltage regulation along with load balancing, neutral current compensation, and harmonics current elimination. A zig-zag/star transformer is used to isolate the voltage source converter, and it is operated as a three-phase four-wire distribution static compensator for power quality improvement in a three-phase four-wire system. In order to reduce the current rating of the voltage source converter, the zig-zag configuration is used in the primary windings of the transformer. The voltage source converter is connected to the secondary windings of the zig-zag/star transformer, and this allows the optimum selection of voltage rating of the voltage source converter. Moreover, this transformer connection provides isolation for the voltage source converter system. The distribution static compensator is implemented using the dSPACE DS1104 R&D controller (dSPACE Inc., Wixom, Michigan, USA) and a slave digital signal processor subsystem based on the TMS320F240 digital signal processor (dSPACE Inc., Wixom, Michigan, USA) to validate the design and the developed control algorithm.

Digital signal processor implementation and performance evaluation of split capacitor, four-leg and three H-bridge-based three-phase four-wire shunt active filters

In this paper a comprehensive study on the three-phase four-wire (3P4W) shunt active power filter (APF) is carried out on the basis of three system configurations. These three two-level voltage source inverter topologies are compared for 3P4W shunt APF, namely, split capacitor (2C), four-leg (4L) and three single-phase H-bridges (3HB). The performance of all three topologies, under an unbalanced non-linear load condition, is evaluated with a detailed digital signal processor (DSP)-based experimental investigation. The steady-state as well as dynamic performance of APF is studied to compensate for current harmonics, reactive power, current unbalance and neutral current. The advantages and limitations offered by each of the topologies are also discussed in brief.

A new smooth quadratic chaotic system and its digital signal processing implementation

Developing and changing nonlinear function of Lorenz chaotic system, a new autonomous chaotic system is generated which contains three smooth quadratic terms of system variables and five equilibriums. The characteristics of five equilibriums are discussed and a fractal dimension is calculated. The features of chaotic system are analyzed in detail using bifurcation diagram and Lyapunov exponent. The period doubling bifurcation of the system can occus. The chaotic system is realized based on digital signal processing. Experimental result shows the effectiveness and feasibility of the theoretical analysis and verifies the behaviors of various attractors.

Close Accord on DWT Performance and Real-Time Implementation for Protection Applications

In this paper, a simpler and faster algorithm of discrete wavelet transform (DWT) for a digital signal processing (DSP) implementation is proposed and intensively tested. Applicability of real-time implementation of this algorithm is verified. The computational frame in this algorithm is independent on the sampling rate, but it depends on the length of the mother wavelet filters. Therefore, signal with any sampling rate can be analyzed with the same computational effort. This implementation algorithm is exploited to investigate the DWT response experimentally. Impact of the mother wavelet, sampling frequency, fault inception angle and the signal transients on the resulted DWT levels is evaluated from the protection perspectives. Considering the DSP channel noise, these factors are strongly affect DWT response especially in high details spike, which the most of the protection applications depended on. Shortcomings of DWT application for protection relays are outlined and corrective recommendations are included.

Real-time implementation of digital signal processing for coherent optical digital communication systems

Digital signal-processing-based coherent optical communication systems are widely viewed as the most promising next-generation long-haul transport systems. One of the biggest challenges in building these systems is the implementation of signal processors that are able to deal with signaling rates of a few tens of giga-samples per second. In this paper, we discuss implementation options and design considerations with respect to hardware realization and DSP implementation.

A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing

This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ; it integrates 97 million transistors and has a peak power consumption of 2.5 W. In order to demonstrate the proposed computational model and the reconfigurable signal processor capabilities in a real test case, a video surveillance motion detection application was implemented in the SoC. When running this application, the device proved able to deliver 120 GOPS dissipating 1.45 W.

DSP implementation of underwater communication using SSB modulation with random carrier frequencies

Underwater acoustic communication is a rapidly growing field of research and applied engineering. It is especially necessary for submarine-ship, submarine-submarine and ship-submarine communications. Recent years have seen rapid advances in DSP (Digital signal processor) architecture technologies, which advances have made it possible for DSP's to be used for applications previously considered unsuitable such as underwater communication. Underwater acoustic communication applications had been performed in an analog environment several times before; however, in this work, it is performed digitally by using DSP. Alternative solutions for underwater communication are presented as well. The presented solution is a more reliable prototype design of underwater acoustic communication that was developed via the transmitter and receiver sides on two identical DSK (DSP Starter Kit) boards by using upper sideband - suppressed carrier (SSB - SC) and random carrier frequencies (8 - 16 kHz). Key words: Underwater acoustic communication, underwater telephone (uwt), digital signal processor.

A Fuzzy Based DSP Implementation for Power Quality Improvement of a Three Phase AC-AC Converter

This paper proposes the use of a fuzzy logic controller (FLC) that serves to enhance the power quality of a three phase ac-ac converter system with a dc link. The FLC is designed so as to shape the load current to a nearly sinusoidal fashion and contribute in improving the input power factor, lowering the total harmonic distortion (THD) and eliminating higher order harmonics. The Digital Signal Processor (DSP), besides generating the PWM gating pulses for the power switches, is programmed to function as PI/FUZZY controller in the feedback loop. The algorithm allows the modulation index to vary, in order to regulate the load voltage. Simulation and experimental results are included to highlight the fact that the scheme also enables to maintain a constant output voltage over a wide range of load variations,

DSP-based flexible digital hysteresis in switched capacitor active power filter

This paper proposes implementation of digital signal processor (DSP) to perform flexible-band digital hysteresis current control in a switched capacitor active power filter (SCAPF). By integrating hysteresis current control with digital-based neural network harmonic detection, the proposed SCAPF forces the supply current to be sinusoidal, to have low current harmonics, and to be in phase with the line voltage. Simulation on MATLAB Simulink verified the controller's algorithm design, and a purpose-built laboratory SCAPF system tested its feasibility.

Digital signal processor against field programmable gate array implementations of space–code correlator beamformer for smart antennas

Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP- and FPGA-based implementations of space–code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Δthetas=2°, whereas it can be achieved within less than 25 µs on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.

A New Multilevel Conversion Structure for Grid-Connected PV Applications

A novel scheme for three-phase grid-connected photovoltaic (PV) generation systems is presented in this paper. The scheme is based on two insulated strings of PV panels, each one feeding the dc bus of a standard two-level three-phase voltage-source inverter (VSI). The inverters are connected to the grid by a three-phase transformer having open-end windings on the inverter side. The resulting conversion structure performs as a multilevel power active filter (equivalent to a three-level inverter), doubling the power capability of a single VSI with given voltage and current ratings. The multilevel voltage waveforms are generated by an improved space-vector-modulation algorithm, suitable for the implementation in industrial digital signal processors. An original control method has been introduced to regulate the dc-link voltages of each VSI, according to the voltage reference given by a single maximum power point tracking controller. The proposed regulation system has been verified by numerical simulations and experimental tests with reference to different operating conditions.

Evaluation of reference current extraction methods for DSP implementation in active power filters

Generation of current references constitutes an important part in the control of active power filters (APFs) used in power system, since any inaccuracy in reference currents yields to incorrect compensation. In this paper, harmonic detection methods for generating reference currents have been evaluated on the basis of three-phase balanced and unbalanced load currents processed in the digital signal processor (DSP). The advantages and disadvantages of several methods found in the literature have been discussed on the basis of simulation results. Three of these methods have been programmed in the TMS320F2812 digital signal processor (DSP) unit and their performances are evaluated from the viewpoint of practical considerations. Finally, instantaneous reactive power method to estimate the APF reference currents is implemented and its practical results obtained under balanced and unbalanced loads are given.

A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter

This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 mum complementary metal-oxide-semiconductor (CMOS) process with an area of 8.8 x 7.2 mm(2) and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment.

Accelerating Integer Neural Networks On Low Cost DSPs

In this paper, low end Digital Signal Processors (DSPs) are applied to accelerate integer neural networks. The use of DSPs to accelerate neural networks has been a topic of study for some time, and has demonstrated significant performance improvements. Recently, work has been done on integer only neural networks, which greatly reduces hardware requirements, and thus allows for cheaper hardware implementation. DSPs with Arithmetic Logic Units (ALUs) that support floating or fixed point arithmetic are generally more expensive than their integer only counterparts due to increased circuit complexity. However if the need for floating or fixed point math operation can be removed, then simpler, lower cost DSPs can be used. To achieve this, an integer only neural network is created in this paper, which is then accelerated by using DSP instructions to improve performance. Keywords—Digital Signal Processor (DSP), Integer Neural Network (INN), Low Cost Neural Network, Integer Neural Network DSP Implementation.

Auditory localization with linear and compression hearing aids

The question of how well hearing-impaired individuals can localize sound (with or without amplification) is still not fully resolved. This study was designed to compare sound localization with two types of hearing-aid (HA) processing, wide dynamic range multichannel compression (WDRMCC) and linear amplification (LA) with compression limiting, during the first 32 weeks of HA use. HAs from two different manufacturers were included to compare different digital signal processing implementations, (1) fast Fourier transform (FFT), necessitating a 10 ms delay, and (2) non-FFT signal processing with a shorter time delay (̃1 ms). We found an initial degradation of sound localization, relative to original unaided performance, for both WDRMCC and LA in both FTT and non-FTT platforms. We found no difference between WDRMCC and LA processing. However, sound localization with non-FFT platform improved consistently throughout 32 weeks of HA use and was better than the original unaided measurements at 16 and 32 weeks. In contrast, localization with the FFT platform showed no consistent change throughout the 32-week test period and remained inferior to original unaided performance. The continuing localization problems present for the FFT, but not the non-FFT, implementations of LA and WDRMCC may be due to its 10-ms processing delay.