Digital Signal Processing Computations Research Articles

High-Definition Dynamic Voltage Restorer Systems Using Equivalent Time Sampling Techniques and Circular Structural Memory Filters

Due to advances in power electronics technology and the evolution of automation devices, the number of electrical devices that are sensitive to power quality is rapidly increasing, and for this reason, users are increasing their demand for high quality. To meet power quality demands, many power conversion devices are used, including dynamic voltage restorers (DVRs). DVRs are recognized as devices that can effectively manage problems such as voltage segments, swells, and harmonics. DVR control requires many samples for harmonic compensation, which has the disadvantage of being complicated to implement due to fast digital signal processing computation and the application of the cyclic discrete Fourier transform. In this paper, a high-precision DVR system configuration is proposed that compensates for harmonics using a periodically equivalent time-interval sampling technique and a novel circular-structured memory filter. The proposed circular-structured multi-pointer memory filter is an effective filter algorithm for high-precision input voltage measurement because it can remove noise and compensate for the delay of the phase angle of the filter in voltage measurement. A simulation and DVR prototype system were built, and the feasibility and effectiveness of the phase angle multi-filter voltage detection method and the compensation method were verified by experiments.

Digital Signal Processing in RadioSolariz Project Using SSE2

This paper aims at elaborating on the digital signal processing techniques used in data manipulation in the radioSolariz solar radio-telescope project. Focus is drawn on the implementation of different digital signal processing algorithms through the use of streaming single instruction – multiple data extensions 2. This complementary instruction set to general purpose personal computer microprocessors offers increased computational power by realizing parallel processing. The benefit is a higher data throughput while lowering the electrical power consumption of the digital signal processing computer. Optimized code fragments are shown along with original code snippets and these are discussed and analyzed. Future work and implementation of other modern parallel processing technologies are envisaged.

High Throughput Spatial Convolution Filters on FPGAs

Digital signal processing (DSP) on field-programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30–60 FPS, while maintaining functional flexibility.

Integrating multicore awareness functions into distribution middleware for improving performance of distributed audio surveillance

This paper describes an approach to improve the performance of the distributed audio-processing functions for audio surveillance systems. In order to increase portability, current distributed audio-processing uses the default capacities offered by the underlying scheduling facilities of the operating system. In this approach, a set of capacities are added to the distribution software that enable the reduction of the distributed processing time of audio frames at the server side by adding functions that utilize the underlying hardware resources including exclusive core reservation. By loosing some generality in the design of the distribution software, it is possible to increase performance and provide better isolation to selected audio tasks in the presence of other competing software tasks. The approach is designed and implemented as well as analyzed on general purpose computers with a server-client architecture using serial scheduling of the audio tasks and parallelizing the digital signal processing computations. The proposed solution is implemented and analyzed showing benefits in performance and robustness over single threaded audio processing. The resulting system is significantly more robust in the presence of other competing software tasks (noise). These results directly yield the possibility to manage more concurrent audio streams at the server side.

A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump

Power consumption has become a critical design criterion for integrated circuits given the growing importance of portable battery-operated devices. A typical CMOS gate driven by power supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ), draws energy equal to C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> during every cycle of operation. We propose a new approach to recycle the charge with an adiabatic charge pump that moves the slower adiabatic components away from the critical path of logic. The critical path of the system, and hence the delay, do not change. This is achieved by overlapping the adiabatic charge pump delays with the computing path logic delays. Many embedded high performance applications such as digital signal processing (DSP), which exhibit datapath parallelism, are ideal candidates for this scheme. The proposed method has been implemented in DSP computations. SPICE simulations-based results indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% (on average 9.94%) with no perceptible loss in performance. The area penalty for these energy savings are in the 1%-2% range, The leakage energy reduction in 45-nm BPTM averages 46%.

Systematic design of high-speed and low-power digit-serial multipliers

Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of the digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bit-level pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bit-parallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes (/spl les/4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/(2W), where W represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in terms of both latency and power consumption.

AdEPar Integrated Simulation and Implementation Environment for DSP

The AdEPar (Advanced Educational Parallel) integrated simulation and implementation environment for Digital Signal Processing (DSP) has been designed and implemented to serve as a test-bed for various scheduling, simulation, and code generation problems as well as a real-time implementation tool for DSP algorithms that could be mapped onto the proposed parallel pipelined architecture. The integrated environment fully exploits all types of concurrency present in DSP algor ithms and addresses practical issues such as processor and memory constraints, architec tural features of DSP processors in the target architectures, debugging of parallel programs, and development of high-level programming environments. The AdEPar software DSP environment is based on object-oriented programming techniques. Because DSP computation objects and graphics objects of AdEPar are separated from each other carefully, the software system portability is guaranteed. This programming approach saves time and effort to develop an environ ment based on a graphical user interface.

A new approach to fixed-coefficient inner product computation over finite rings

Inherently parallel arithmetic based on the residue number system (RNS) lends itself very well to implementation of high-speed digital signal processing (DSP) hardware. In most cases, DSP computations can be decomposed to the inner product form Y=/spl Sigma//sub i=0//sup N-1/C/sub i/X/sub i/. Therefore, implementation of the inner product computation over finite rings is of paramount importance for RNS-based DSP hardware. Recently, periodic properties of residues of powers of 2 have been found useful in designing residue arithmetic circuits. This paper presents a deeper insight to the periodicity concepts by applying abstract algebra and number theory methods. Advantage is taken of the fact that the set Z/sub m//sup +/={1, 2, ..., m-1} splits completely, with respect to some g/spl isin/Z/sub m//sup +/, into sets which are closed under multiplication by g modulo m. Properties of such a decomposition of Z/sub m//sup +/ are investigated and the theory is applied to develop new fixed-coefficient inner product circuits for finite-ring arithmetic. The new designs are almost exclusively composed of full adders and they can easily be pipelined to achieve very high throughput. A VLSI implementation study of the new inner product circuits is presented. It shows that, compared with the best method known to date, both smaller area requirements and higher throughput are achieved.

Doubly pipelined CORDIC array for digital signal processing algorithms

Abstract In this paper, we present a doubly pipelined VLSI CORDIC array processor for digital signal processing computations. The basic notion of doubly pipelined CORDIC computation will be introduced first. Then, some potential applications to digital signal processing problems will be discussed. Specifically, we shall demonstrate how this novel architecture can be applied to compute discrete Fourier transform and fast Fourier transform, to implement lattice filters, to solve Toeplitz systems, as well as matrix QR/LQ factorizations. It is shown that by adopting secondary pipelining, about one third of the hardware can be saved, and under certain cases, the throughput of the entire CORDIC processor array may be doubled.

TMS 320—a step forward in digital signal processing

Despite the numerous advantages of digital signal processing (DSP), and the existence of a wealth of sophisticated algorithms, the widespread application of DSP has been hindered by a shortage of cost-effective digital hardware for volume use. Now, with the availability of low-cost high-speed VLSI circuits, such as the Texas Instruments TMS320, the virtues and power of DSP are ready for realtime signal processing applications. Development of the single-chip TMS320 DSP computer began in the late 1970s. The architecture, key novel features, instruction set and capabilities of this device are examined. Support software and hardware development tools for the TMS320 are also included with some of its applications. Typical areas of application of the TMS320 include speech signal processing, telecommunications, robotics, radar signal and sonar signal processing, seismology, image processing, audio recording and reproduction, biomedical instrumentation, acoustic noise measurements and automatic test equipment.