Digital Signal Processing Applications Research Articles

Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

Design Wallace Tree Multiplier Using Reversible Gates

Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications

As technology advances at a rapid pace, there is an increasing need for real-time digital signal processing (DSP) applications that are efficient and swift. DSPs, or digital signal processors, are crucial components of several engineering disciplines. For processes like convolution and Fourier transforms in DSPs, rapid multiplication is essential. Multiplication is one of the basic mathematical operations used by all applications. Many different multiplier designs have been developed to boost their speed. When compared to array and booth multipliers—the products of decades of hard research—vedic multipliers are among the fastest and lowest power multipliers. The sixteen sutras, or algorithms, that the Vedic Multiplier uses are primarily logical procedures. They are the fastest and most effective because several of them have been proposed using the Urdhava Tiryakbhyam sutra. The purpose of this study is to provide an overview of the numerous biomedical applications of Vedic Multiplier in the wide field of digital signal processing, including denoising of Electrocardiogram (ECG) and Electroencephalogram ( EEG) signal. Particular attention is paid to how current Vedic Multiplier designs have been altered to increase speed and performance metrics.

Performance Analysis of Vedic Multiplier in Signal Processing Applications

The demand for quick and effective real-time digital signal processing (DSP) applications has increased due to the rapidly advancing technology. Digital signal processors, or DSPs, are essential to several engi- neering specialties. In DSPs, quick multiplication is crucial for operations like Fourier transformations and convolution. One of the fundamental arithmetic processes required by all applications is multiplication. To increase their speed, numerous multiplier designs have been created. Vedic multipliers are among the quick- est and lowest power multipliers compared to array and booth multipliers which are the result of decades of intensive research. The Vedic Multiplier works with sixteen sutras, or algorithms, most of which are for logical processes. Since several of them have been proposed utilizing the Urdhava Tiryakbhyam sutra, they are the fastest and most efficient. This paper's goal is to summarise the many uses of Vedic Multiplier in the broad field of digital signal processing such as image processing, with a focus on the various ways that Vedic Multiplier designs that are now in use have been modified to improve speed and performance metrics.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

Analysis of Eeg Data Using Different Techniques of Digital Signal Processing

This paper explores the application of digital signal processing (DSP) techniques in the examination of electroencephalogram (EEG) data. DSP encompasses a collection of mathematical algorithms designed to employ signals, such as EEG recordings, and finds application in diverse domains, including sleep medicine, neuroscience, and biomedical engineering. Employing DSP methods for EEG data analysis enables the extraction of pertinent insights from EEG signals, the identification of event-related patterns, and the enhancement of diagnostic and therapeutic practices across various disciplines. This article provides an overview of prevalent DSP methodologies employed in EEG signal processing, encompassing filtering, power spectral analysis, wavelet analysis, independent component analysis, and artifact removal.

Implementation of Systolic Multiplier Using Hybrid Multiplexer Dependent Adder

Multipliers are basic building blocks in various integrated circuits like microprocessors, micro controllers, and ALUs. The existing multipliers suffer from high power consumption and inefficient use of hardware resources. They often rely on traditional adder structures that are not tailored for specific operations, leading to suboptimal performance. Additionally, their fixed architectures limit adaptability and scalability in different applications. So, the proposed approach offers enhanced computational efficiency and reduced power consumption compared to conventional multiplier designs. By integrating multiplexer-dependent adders into the systolic array, the proposed method optimizes resource utilization and delivers improved performance for various arithmetic operations. This integration allows for dynamic selection of adder types based on the specific multiplication operation, significantly reducing power consumption and latency. By adapting the hardware resources to computational needs, the method achieves higher efficiency and flexibility, making it suitable for a wide range of applications in digital signal processing and data processing systems.

Digital Signal Processing Oriented Electronic Communication Engineering Applications and Practices

This paper first describes the applications of digital signal processors in software radio, speech compression coding, modems and GPS systems, demonstrating the versatility of digital signal processors in practical communication systems. Next, digital signal processing oriented electronic communication practices are presented in the system design section to design high performance communication systems for specific communication needs and environmental conditions. The digital signal processing platform used in the platform architecture is optimized for signal processing and data transmission. The BER is 0.008% when the signal-to-noise ratio is -10 dB. The time complexity of digital signal processing is 7.2 ms when the number of communication nodes is 1000. It shows that digital signal processing oriented electronic communication engineering is important for improving the performance, reliability and efficiency of communication systems.

Digital Signal Processing Approaches in the field of Genomics: A Recent Trend

Digital signal processing (DSP) techniques have emerged as powerful tools in the field of genomics, enabling researchers to extract valuable insights from complex genetic data. This research paper presents a comprehensive analysis of the recent trends and advance- ments in applying DSP approaches to genomics. The objective is to provide an overview of the transformative role of DSP in genomic data analysis, variant calling, and interpretation. By leveraging DSP methods such as filtering, feature extraction, time-frequency analysis, and machine learning algorithms, researchers can enhance the quality of genetic signals, identify genetic variants, and gain a deeper understanding of genomic processes. The paper highlights key applications of DSP in genomics, including DNA sequence analysis, RNA expression pro- filing, epigenetics, and genome-wide association studies. Additionally, the challenges associated with applying DSP techniques in genomics, such as signal noise, data in- tegration, and computational complexity, are discussed. This research paper serves as a valuable resource for researchers, bioinformaticians, and geneticists seeking to harness the power of DSP in genomics, advancing our knowledge of genetic diseases and paving the way for personalized medicine and precision healthcare. Keywords: Digital signal processing, Genome analysis, Feature extraction, DNA sequence analysis, RNA expression profiling.

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

Low power CNTFET-based ternary multiplier for digital signal processing applications

Abstract Multiplication is a fundamental arithmetic process, although it necessitates more hardware resources. Researchers in advanced technology attempted to boost the speed and lower the power in digital signal processing applications by utilizing multipliers. The majority of digital signal processing applications demanded increased speed. In addition, ternary logic based on CNTFETs is a feasible alternative for Si-MOSFETs. The article proposes a ternary multiplier, which is designed using proposed ternary logical and combinational circuits that includes STI, TNAND, TNOR, and ternary decoder. The proposed and existing designs are simulated, compared, and analysed on the parameters of delay, average power, and noise using the HSPICE simulator. Therefore, the results show 10%, 81% and 81% improvement in delay, average power, and PDP respectively for proposed TMUL. The noise margin of the proposed TMUL is increased up to 54% over existing circuits. The proposed TDecoder, STI, TNAND, and TNOR are 95%, 97%, 81%, and 95% more energy efficient than existing designs, respectively.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

FPGA Implementation of DFT Processor using Vedic Multiplier

Many a times Mathematical computations are easier in frequency domain than time domain. Discrete Fourier transform (DFT) is a tool to convert signals from time domain to frequency domain which is widely used mainly in Digital Signal and Image Processing applications. Fast Fourier Transform (FFT) is a method to find DFT in time constraint applications which is affected by number of complex multiplier. In this paper 16-bit DFT using Vedic Multiplier, a high- speed multiplier is proposed with an objective to replace conventional complex multiplier and to decrease computation time. The proposed system is implemented in Virtex-4 FPGA and the results show that FFT using Urdhva Tiryakbhyam algorithm of Vedic multiplier is faster than other methods of DFT

An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm

ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

Enhancing Computer Digital Signal Processing through the Utilization of RNN Sequence Algorithms

With the increase in computing power and the availability of large amounts of data, deep learning techniques, especially convolutional neural networks (CNNS) and recurrent neural networks (RNNS), have become important tools for processing complex signals. These methods show excellent performance in speech recognition, image processing, natural language processing and so on. In this paper, we explore the application of recurrent neural network (RNN) sequence algorithms in the field of computer digital signal processing, highlighting current artificial intelligence techniques and their capabilities in solving complex signal processing problems. First, the paper reviews the basic principles and development of deep learning and RNN sequence algorithms, highlighting the advances these advanced technologies have made in simulating the way the human brain processes information. The practical application and effect of RNN sequence algorithm in computer digital signal processing are demonstrated through experimental data. By comparing with traditional algorithms, we demonstrate the efficiency and accuracy of RNN in processing complex signals, such as speech recognition in noisy environments and real-time video data processing. The experimental data not only demonstrate the effectiveness of RNNS in this field, but also highlight the unique advantages of deep learning methods when dealing with large and high-dimensional data. Through these empirical studies, this paper aims to provide researchers and engineers with an in-depth understanding of the potential of RNNS in digital signal processing applications, and looks forward to the future development direction of artificial intelligence technology in this field.

Design of 4-bit absolute value detector with low energy

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

Design and implementation of hybrid logic based MAC unit using 45 nm technology

Digital signal processing algorithms, at times, necessitate the execution of a substantial quantity of mathematical operations to speed up and iterate upon a particular data set. Numerous digital signal processing (DSP) applications impose limitations on delay, necessitating the accomplishment of DSP operations within a predetermined timeframe, hence rendering deferred processing not feasible. Therefore, digital signal processing (DSP) necessitates a multiplier and accumulator (MAC) unit that exhibits fast speed, high throughput, and low power consumption. This research aims to develop and execute a low-power MAC unit utilising a hybrid logic technique to achieve power efficiency. A MAC unit has been purposefully designed with suitable geometries to provide optimised power, area, and delay characteristics. Estimating the delay in the MAC unit depends upon data flow analysis between the MAC blocks, explicitly focusing on low-power concerns. The developed hybrid adder cell possesses several advantageous characteristics, including a high operational speed, low power consumption, minimal transistor count. The MAC architecture uses a 45 nm CMOS technology with the Mentor Graphics tool. This research additionally examines different designs of multipliers and adders that are well-suited for the execution of high throughput signal processing while simultaneously achieving low power consumption. The registers in the MAC have been implemented in GDI logic using Multi Bit Flip flops technique to achieve low power operation. The entire MAC circuitry operates on a voltage supply of 1 V. The hybrid logic MAC architecture that has been developed demonstrates a significant decrease in area consumption, amounting to a reduction of 68 % when compared to the typical CMOS logic design. Hybrid logic demonstrates a power consumption that is 92 % better compared to CMOS logic.

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

Phased array antenna controlled by FPGA-ARM Cortex-M Processor

This paper discusses the architecture of an adaptive transmitting antenna array that allows highly flexible beamsteering. Antenna arrays are used in many digital signal processing applications due to their ability to locate signal sources. The Direction of Arrival (DOA) estimation is a key task of array signal processing, with the Taguchi method and Multiple Signal Classification (MUSIC). Although various algorithms have been developed for DOA estimation, their high complexity prevents their use in real-time applications. In this paper, we design and develop an implementation using Field Programmable Gate Array (FPGA Artix-7), which is the most widely used ARM processor in embedded systems. The antenna array is digitally controlled with the phases synthesized by the Taguchi method.