Digital Signal Processing Algorithms Research Articles

OptiComm-GPT: a GPT-based versatile research assistant for optical fiber communication systems

With the increasing capacity and complexity of optical fiber communication systems, both academic and industrial requirements for the essential tasks of transmission systems simulation, digital signal processing (DSP) algorithms verification, system performance evaluation, and quality of transmission (QoT) optimization are becoming significantly important. However, due to the intricate and nonlinear nature of optical fiber communication systems, these tasks are generally implemented in a divide-and-conquer manner, which necessitates a profound level of expertise and proficiency in software programming from researchers or engineers. To lower this threshold and facilitate professional research easy-to-start, a GPT-based versatile research assistant named OptiComm-GPT is proposed for optical fiber communication systems, which flexibly and automatically performs system simulation, DSP algorithms verification, performance evaluation, and QoT optimization with only natural language. To enhance OptiComm-GPT’s abilities for complex tasks in optical fiber communications and improve the accuracy of generated results, a domain information base containing rich domain knowledge, tools, and data as well as the comprehensive prompt engineering with well-crafted prompt elements, techniques, and examples is established and performs under a LangChain-based framework. The performance of OptiComm-GPT is evaluated in multiple simulation, verification, evaluation, and optimization tasks, and the generated results show that OptiComm-GPT can effectively comprehend the user’s intent, accurately extract system parameters from the user’s request, and intelligently invoke domain resources to solve these complex tasks simultaneously. Moreover, the statistical results, typical errors, and running time of OptiComm-GPT are also investigated to illustrate its practical reliability, potential limitations, and further improvements.

Alamouti-coded DSP algorithm with a simplified PTBC decoder for next-generation optical access networks

The use of Alamouti-coded polarization-time block code (A-PTBC) in combination with a simple single polarization coherent receiver enables phase-diverse coherent detection without any optical polarization tracking. However, applying this technique to high-speed single-carrier systems is not straightforward, as it requires specialized digital signal processing (DSP) algorithms for data recovery, which increases DSP complexity. In this paper, we propose a novel Alamouti-coded coherent algorithm designed to significantly reduce the complexity of the receiver DSP for data recovery. The proposed algorithm achieves the comparable performance to the conventional algorithm but requires only half the number of necessary equalizers for data recovery. We validate its performance through simulations and also experimentally demonstrate a 100 Gb/s 16-quadrature amplitude modulation (QAM) single-carrier coherent system employed the single-polarization coherent receiver over 20 km of standard single-mode fiber (SMF). Through the performance verification, the coherent system with the proposed algorithm exhibits performance comparable to that of the conventional Alamouti-coded coherent system and achieves a power budget of 34 dB when the transmit launch power is set to 7 dBm at a Bit Error Rate (BER) of 1 × 10−2 for 0-20 km fiber transmission.

Разработка и исследование подхода к обработке сигналов цифровых измерительных трансформаторов тока и напряжения

During the development of secondary systems of stations and substations, including relay protection, automation, control, electricity metering, etc., qualitative changes have recently occurred due to the introduction of digital technologies. The introduction of digital technologies is supported by innovative development programs such as “Digital Transformation 2030”. The introduction of digital technologies is associated with the use of digital data transmission channels according to uniform standards. Projects of “digital substations” are being actively implemented with the transmission of digital information at all levels, including the primary equipment, the transmission of information both from current and voltage measuring transformers, and from switching devices. Currently, digital instrument transformers are actively being developed and implemented, in which information about measured currents and voltages is presented in digital code. New approaches to measure primary currents and voltages, and transmit information pose new challenges, and open prospects for improving signal processing methods used for relay protection purposes. Thus, the relevant aim of the study is the development and research of approaches to digital processing of signals of digital instrument current and voltage transformers. To solve the problems posed within the framework of this study, analytical and numerical solution methods have been used. Numerical methods are applied using software products such as MathCAD and the Python programming language to generate signals and display them on graphs. To substantiate the reliability, verification of the results obtained by different methods is carried out. The authors have formulated an approach to digital processing of signals obtained using current sensors of a digital instrument transformer. The authors have studied the approach to determine synchronized current vector values by processing information received from primary current converters. The characteristics of the algorithm for obtaining a vector have been analyzed and the dependences of errors on the influence of distorting factors have been plotted. The proposed approach is a development of the existing approach to obtain a vector by getting information from current sensors operating on different physical principles. The results show the advantages of the proposed method. The proposed digital signal processing algorithm is more technically expensive since it contains at least two metrologically calibrated measuring channels instead of one. However, all other things being equal, it allows to increase the accuracy and speed of the digital processing algorithms taken as a prototype. The results obtained can be used to formulate algorithms for measuring relay protection devices.

LUAEMA: A Loop Unrolling Approach Extending Memory Accessing for Vector Very-Long-Instruction-Word Digital Signal Processor with Multiple Register Files

Loop unrolling can provide more instruction-level parallelism opportunities for code and enables a greater range of instruction pipeline scheduling. In high-performance very-long-instruction-word (VLIW) digital signal processors (DSPs), there are special registers to address. To further improve the instruction-level parallelism of code for such DSPs by making full use of these registers, in this paper, we propose a more effective loop unrolling approach through extending memory accessing (LUAEMA). In this approach, the final unrolling factor is computed by a model in which every register kind and every memory accessing operation are considered. For basic digital signal processing algorithms, the unrolling factor under the LUAEMA is larger than that under the conventional loop unrolling approach. We also provide the opportunity to reduce the number of instructions in a loop during the code transformation of loop unrolling. The experimental results show that the loop unrolling approach proposed in this paper can achieve an average speedup ratio ranging from 1.14 to 1.81 compared with the conventional loop unrolling approach. For some algorithms, the peak speedup ratio is up to 2.11.

Design of Intelligent Control Systems for Layered Water Injections in Oilfields

With rapid socio-economic growth and increased energy demand, exploration and exploitation of oil and gas resources have become crucial. Long-term exploitation leads to problems such as pressure drop and production reduction in oil fields, and water injection technology has become a common method to improve these problems. The traditional direct water injection for oil extraction has problems such as high injection cost and low oil recovery efficiency. Therefore, an intelligent control system for different oilfield reservoirs is needed. This study focuses on the layered water injection intelligent system based on advanced sensor technology, digital signal processing and intelligent algorithms. The article reviews the advantages of layered water injection system and the current research status, designs an intelligent control structure including hardware circuits and modular software processes, and adopts adaptive particle swarm optimization algorithm as the core of intelligent control.

THE DESIGN OF THE PIPELINED RISC-V PROCESSOR WITH THE HARDWARE COPROCESSOR OF DIGITAL SIGNAL PROCESSING

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.
 In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.
 Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.
 Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.
 Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.
 Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

Improving Utilization of Dataflow Unit for Multi-Batch Processing

Dataflow architectures can achieve much better performance and higher efficiency than general-purpose core, approaching the performance of a specialized design while retaining programmability. However, advanced application scenarios place higher demands on the hardware in terms of cross-domain and multi-batch processing. In this article, we propose a unified scale-vector architecture that can work in multiple modes and adapt to diverse algorithms and requirements efficiently. First, a novel reconfigurable interconnection structure is proposed, which can organize execution units into different cluster typologies as a way to accommodate different data-level parallelism. Second, we decouple threads within each DFG node into consecutive pipeline stages and provide architectural support. By time-multiplexing during these stages, dataflow hardware can achieve much higher utilization and performance. In addition, the task-based program model can also exploit multi-level parallelism and deploy applications efficiently. Evaluated in a wide range of benchmarks, including digital signal processing algorithms, CNNs, and scientific computing algorithms, our design attains up to 11.95× energy efficiency (performance-per-watt) improvement over GPU (V100), and 2.01× energy efficiency improvement over state-of-the-art dataflow architectures.

Low-complexity and low-latency equalization technique - probabilistic noise cancellation.

Both inside data centers (DCs) and in short optical links between data centers (DC campuses), intensity-modulation and direct-detection (IMDD) systems using four-level pulse amplitude modulation (PAM4) will dominate this decade due to low transceiver price and power consumption. The next DC transceiver generation based on 100 Gbaud PAM4 will require advanced digital signal processing (DSP) algorithms and more powerful forward error correction (FEC) codes. Because of bandwidth limitations, the conventional DC DSP based on a few-tap linear feed-forward equalizer (FFE) is likely to be upgraded to more complex but still low-complexity Volterra equalizers followed by a noise whitening filter and either a maximum likelihood sequence estimation (MLSE) or a maximum a posteriori probability (MAP) algorithm. However, stringent power consumption and latency requirements may limit the use of complex algorithms such as decision feedback equalizer (DFE) or MLSE/MAP in DC networks (DCN). In this paper, we introduce a low-complexity, low-latency algorithm based on a feedforward structure, yielding a performance between DFE and MLSE. We call the novel equalization algorithm probabilistic noise cancellation (PNC), since it weights noise patterns based on their probabilities in the presence of bandwidth limitations. The probabilistic weighting is efficiently exploited in correcting correlated errors caused by noise coloring in the FFE.

High key rate continuous-variable quantum key distribution using telecom optical components

Quantum key distribution (QKD) is one quantum technology that can provide secure encryption keys for data transmission. The secret key rate (SKR) is a core performance indicator in QKD, which directly determines the transmission rate of enciphered data. Here, for the first time, we demonstrate a high-key-rate Gaussian-modulated continuous-variable QKD (CV-QKD) using telecom optical components. The framework of CV-QKD over these components is constructed. Specifically, the high-rate low-noise Gaussian modulation of coherent states is realized by a classical optical IQ modulator. High-baud low-intensity quantum signals are received by an integrated coherent receiver under the shot-noise limit. A series of digital signal processing algorithms are proposed to achieve accurate signal recovery and key distillation. The system can yield a high asymptotic SKR of 10.37 Mbps within 20 km standard telecom fiber, and the secure distance can exceed 100 km. This result confirms the feasibility of CV-QKD with state-of-the-art performance using telecom optical components. Besides, due to the ease of integrating these discrete components, it provides a high-performance and miniaturized QKD solution for the metropolitan quantum network.

Optical access networks for fixed and mobile applications [Invited Tutorial

Optical access networks are playing a more critical role in providing diverse emerging applications for human- and machine-type communications. With the ever-growing demand for higher capacity, higher fidelity, and massive connections, numerous innovative transmission schemes and digital signal processing algorithms have been proposed in a cost-effective way. Here, we focus on two main scenarios, namely, fixed and mobile access. For the fixed access network, the solutions are categorized into direct detection, simplified coherent detection, and self-coherent detection. For the mobile fronthaul, we classify the schemes according to the functional split, including the analog radio-over-fiber, common public radio interface (CPRI), enhanced CPRI (eCPRI), and integrated and hybrid digital/analog-over-fiber interfaces. This tutorial provides an overview of the enabling technologies for fixed and mobile applications in the fifth-generation (5G) era and beyond.

SIMULATION MODEL OF AN ADARTIVE DIGITAL FILTER BASED ON THE LEAST SQUARES METHOD

In accordance with contemporary requirements in the fields of mobile and embedded telecommunications and electronics, there is a growing need for faster, smaller, and energy-efficient digital electronic devices (DEDs). These devices include microcontrollers, digital signal processors, and programmable logic integrated circuits (FPGAs).
 Utilizing DEDs involves the hardware execution of advanced digital signal processing (DSP) algorithms tailored to the specific architecture of the electronic device. To expedite the design process when directly implementing DSP algorithms in hardware, simulation models are generated to facilitate optimizing the design during the creation of the programming component for FPGAs.
 The paper discusses the outcomes of an investigation into an adaptive filter (AF) model that relies on the recursive least squares method (RLS). During the simulation, an analysis of the time and frequency parameters of the AF model was conducted. It was determined that the quality of the filtering process reaches a plateau at the 28th order, and further increasing the AF order does not lead to a significant improvement in signal filtering. Instead, it results in an increased demand for hardware resources. Furthermore, during the verification of the proposed simulation model, an AF-based noise reduction system was simulated. The total harmonic distortion (THD) level for the built-in AF unit was found to be 1.05 % that serves as confirmation of the effectiveness of the developed AF unit.
 Therefore, through this investigation, the most suitable order for the AF has been identified. This choice will enable a more effective utilization of FPGA resources when implementing the AF in hardware. The study results validate the accuracy and effectiveness of the hardware-centric simulation model developed, while also demonstrating the hardware-oriented architecture of the adaptive RLS filter for its forthcoming implementation on FPGA.

Hardware Implementation of the Digital Signal Processing Algorithms in Recurrent Signal Processor on FPGA

Hardware Implementation of the Digital Signal Processing Algorithms in Recurrent Signal Processor on FPGA

Non-orthogonal multiple access in a radio over fiber link based on optical-domain power allocation.

Non-orthogonal multiple access (NOMA) in a radio over fiber (RoF) link based on optical-domain power allocation is proposed and demonstrated. The NOMA is implemented at the RoF transmitter where two spectrum-overlapped microwave vector signals with an identical power level are modulated on an optical carrier to generate two orthogonally polarized optical signals. By passing the optical signals through a polarization controller (PC) and a polarizer, the power levels of the two optical signals are controlled to achieve optical power allocation (OPA). The optical signals are then transmitted over a fiber to the receiver. Since the power levels of the two microwave vector signals applied to the modulator are identical and the power allocation is implemented in the optical domain, the nonlinearity due to the higher-power input microwave vector signal is reduced, leading to an increase in the dynamic range. At the receiver, the two optical signals are detected at a photodetector (PD). To demultiplex the two microwave vector signals, a digital signal processing (DSP) algorithm is developed. The proposed approach is evaluated experimentally. The results show that the transmission performance in terms of error vector magnitude (EVM) is improved thanks to the increased dynamic range.

Research on electronic stethoscope system and signal processing algorithm

Stethoscopes have an important role in non-invasive diagnosis of cardiovascular and respiratory diseases, digestive diseases, and other kinds of diseases. The emergence of high-end diagnostic devices and new diagnostic methods have caused the status of the stethoscope to decline. However, stethoscope has the advantages of simple operation, mature auscultation theory and low cost, and thus is still widely used in medical diagnosis. This paper first introduces the design and application of electronic stethoscope solutions based on contact sensors and air coupling sensors, and then introduces advanced algorithms for digital signal processing for the diagnosis and treatment of different diseases, including heart sound noise reduction algorithm, heart sound segmentation algorithm and heart sound feature extraction and recognition algorithm. Finally, this paper summarizes the application of the electronic stethoscope system in medical testing, and its future development direction. In summary, the electronic stethoscope system is a reliable medical testing tool, which can convert sound signals into digital signals through complex signal processing algorithms for more accurate detection of human physiological parameters. The research of this paper will be of great value to the research and application of electronic stethoscopes.

Design and implementation of hybrid logic based MAC unit using 45 nm technology

Digital signal processing algorithms, at times, necessitate the execution of a substantial quantity of mathematical operations to speed up and iterate upon a particular data set. Numerous digital signal processing (DSP) applications impose limitations on delay, necessitating the accomplishment of DSP operations within a predetermined timeframe, hence rendering deferred processing not feasible. Therefore, digital signal processing (DSP) necessitates a multiplier and accumulator (MAC) unit that exhibits fast speed, high throughput, and low power consumption. This research aims to develop and execute a low-power MAC unit utilising a hybrid logic technique to achieve power efficiency. A MAC unit has been purposefully designed with suitable geometries to provide optimised power, area, and delay characteristics. Estimating the delay in the MAC unit depends upon data flow analysis between the MAC blocks, explicitly focusing on low-power concerns. The developed hybrid adder cell possesses several advantageous characteristics, including a high operational speed, low power consumption, minimal transistor count. The MAC architecture uses a 45 nm CMOS technology with the Mentor Graphics tool. This research additionally examines different designs of multipliers and adders that are well-suited for the execution of high throughput signal processing while simultaneously achieving low power consumption. The registers in the MAC have been implemented in GDI logic using Multi Bit Flip flops technique to achieve low power operation. The entire MAC circuitry operates on a voltage supply of 1 V. The hybrid logic MAC architecture that has been developed demonstrates a significant decrease in area consumption, amounting to a reduction of 68 % when compared to the typical CMOS logic design. Hybrid logic demonstrates a power consumption that is 92 % better compared to CMOS logic.

Integrate-and-fire circuit for converting analog signals to spikes using phase encoding * *The authors would like to thank Alexander Lenz and Susanne Junghans for their expertise and input, which was very valuable for implementing and testing the designed circuit. The authors would also like to thank the Technical University of Dresden for granting them access to the SpiNNaker 2 chip

Processing sensor data with spiking neural networks on digital neuromorphic chips requires converting continuous analog signals into spike pulses. Two strategies are promising for achieving low energy consumption and fast processing speeds in end-to-end neuromorphic applications. First, to directly encode analog signals to spikes to bypass the need for an analog-to-digital converter. Second, to use temporal encoding techniques to maximize the spike sparsity, which is a crucial parameter for fast and efficient neuromorphic processing. In this work, we propose an adaptive control of the refractory period of the leaky integrate-and-fire (LIF) neuron model for encoding continuous analog signals into a train of time-coded spikes. The LIF-based encoder generates phase-encoded spikes that are compatible with digital hardware. We implemented the neuron model on a physical circuit and tested it with different electric signals. A digital neuromorphic chip processed the generated spike trains and computed the signal’s frequency spectrum using a spiking version of the Fourier transform. We tested the prototype circuit on electric signals up to 1 kHz. Thus, we provide an end-to-end neuromorphic application that generates the frequency spectrum of an electric signal without the need for an ADC or a digital signal processing algorithm.

Программно-аппаратные методы подавления электроакустической обратной связи в радиоэлектронных системах аудиомониторинга

The purpose of the article is to analyze software and hardware methods of suppression of electroacoustic feedback in radioelectronic systems of audio monitoring and television production. The work shows a numerical analysis of signal methods for compensating positive feedback of radio acoustics, as well as an architectural DSP solution for constructing a notch equalization ruler with auto-tracking multitonal sound suppression based on an ADAU1701 audio processor. Methods: algorithms of digital signal processing, theory of stability of sound-amplifying and sound-picking radio systems, methods of signal radio acoustics, theory and methods of analysis of self-oscillating circuits, vector theory of the sound field. Results: the causes of electroacoustic feedback have been identified; an adaptive algorithm for suppressing electroacoustic feedback has been proposed and investigated; an experiment with the use of an electroacoustic feedback auto-suppression submodule has been analyzed.

Ultrasonic vibration measurement using heterodyne interferometry and SDR phase meter

Ultrasonic vibration measurement and the development of ultrasonic vibration sensors have a significant impact on underwater pattern detection, providing good support for the exploitation and usage of marine resources. Advanced digital signal processing algorithms improve mechanical displacement measurements using ultrasonic speed and pm-level interferometers in real-time. In recent years, developing digital algorithms and employing low-cost software-defined radio (SDR) software applied to communication systems and other general-purpose systems with flexible solutions are essential in modern industrial applications. Specifically, the SDR can be consistent with real-time phase-change measurements of MHz-frequency interference signals for a heterodyne interferometer. This paper combines a heterodyne interferometer and a real-time SDR phase meter, demonstrating an ultrasonic vibration instrument's high-speed vibrating measurement capabilities. A double-pass interferometer is implemented to produce interference signals modulated with a sine waveform phase change associated with a tool's ultrasonic vibrating displacement, calculated by the phase meter's quadrature demodulation algorithm. The measurement results show that the system detects the sine-wave vibration trajectory generated by the vibrator at a frequency of 20 kHz and an amplitude of ~460 nm. The principle of the measurement system, instrumentations, experiments, and results are discussed in the paper.

MATHEMATICAL FRAMEWORK FORMULATION AND IMPLEMENTATION FOR HYPERSPECTRAL AEROSPACE IMAGES PROCESSING

This paper proposes a preprocessing algorithm for aerospace hyperspectral images based on a mathematical apparatus effectively applied in pre-compression transformation problems. In particular, several methods have been analyzed for hyperspectral image (signal) preprocessing from the point of view of digital signal processing algorithms. These mathematical methods are used for problems of filtering signals from noise of different natures and for compression and restoration of signals after their transmission through communication channels. The results of comparative analysis of preparatory processing of lossy compression algorithms based on wavelet analysis, discrete and orthogonal transforms are also given, demonstrating minimization of loss level of reconstructed decoded images. The performance of the proposed preprocessing algorithms with quality metrics is presented to evaluate the quality of the reconstructed hyperspectral aerospace images. The results of this study can be applied and used in the tasks of special processing of hyperspectral images, as well as fundamental knowledge of mathematical apparatuses of the proposed orthogonal preprocessing, considering the specificity of the data which is very important in obtaining images ready for compression for the subsequent identification of objects of the Earth's surface and using such mathematical transformations at the hyperspectral image preprocessing stage before compression provides efficient archiving of the obtained data, while reducing the communication channel load. Through the use of quality metrics of the reconstructed images, the preprocessing algorithm provides an understanding of the threshold of the peak signal-to-noise ratio value and the efficiency of its application to calculate and minimize the loss rate.

100Gb/s coherent optical secure communication over 1000 km based on analog-digital hybrid chaos.

In recent years, the transmission capacity of chaotic secure communications has been greatly expanded by combining coherent detection and multi-dimensional multiplexing. However, demonstrations over 1000 km fiber are yet to be further explored. In this paper, we propose a coherent optical secure transmission system based on analog-digital hybrid chaos. By introducing an analog-digital converter (ADC) and a bit extraction into the feedback loop of entropy source, the broadband analog chaos is converted into a binary digital signal. This binary digital signal is then mapped to a 65536-level pulse amplitude modulation (PAM) signal and injected into the semiconductor laser (SL) to regenerate the analog chaos, forming a closed loop. The binary digital signal from the chaos source and the encrypted signal are transmitted via wavelength division multiplexing (WDM). By using conventional digital signal processing (DSP) algorithms and neural networks for post-compensation, long-haul high-quality chaotic synchronization and high-performance secure communication are achieved. In addition, the probability density distribution of the analog chaotic signal is effectively improved by adopting the additional higher-order mapping operation in the digital part of the chaos source. The proof-of-concept experimental results show that our proposed scheme can support the secure transmission of 100 Gb/s quadrature phase shift keying (QPSK) signals over 1000 km of standard single-mode fiber (SSMF). The decrypted bit error rate (BER) reaches 9.88 × 10-4, which is well below the 7% forward error correction (FEC) threshold (BER = 3.8 × 10-3). This research provides a potential solution for high-capacity long-haul chaotic optical communications and fills the gap in secure communications based on analog-digital hybrid chaos.