Digital Signal Processing Algorithms Research Articles

Enhanced Performance Analysis of 120 Gbps Single‐Channel IQ Modulation Based PDM‐FSO Transmission System Using 64‐QAM Signals

ABSTRACTThe ever‐augmenting demand of data channel‐bandwidth by the end users has resulted in the exploration of new transmission techniques for wireless transmission networks. In this work, we have demonstrated the modeling of a single‐channel free space optics (FSO) transmission system by employing polarization‐division‐multiplexing (PDM) technique. Further, in‐phase‐quadrature modulation (IQM) has been used to increase the transmission efficiency of the system. To decrease the baud‐rate of the system, we have proposed the use of 64‐level quadrature amplitude modulation (QAM) signals. The net transmission rate of the system is 120 Gbps with a baud‐rate of 10 Gbps. Furthermore, the overcome the signal degradation of the 120 Gbps signal propagating through atmospheric channel, we have reported the use of advanced digital signal processing (DSP) algorithms. The system's performance is investigated for adverse external climate weather conditions and the results reported show reliable 120 Gbps data transmission along range between 870 m and 16.25 km with good performance of BER and EVM 7.5%.

Polymer-metal film induced ultrahigh output TVNG and self-powered intelligent sensor system assisted by EEMD

Tribovoltaic nanogenerators (TVNGs) based on tribovoltaic effect can output DC current directly, and has the advantages of high output current density and low internal resistance. While TVNGs have been restricted by its low output voltage and power. Herein, we have developed a metal-polymer film with a micro-uneven structure on the surface, much higher corrosion resistance and wear resistance than metal. On this basis, a centimeter-level sliding structure metal-EP/GaN-TVNG has been fabricated, which shows a high and stable long-term DC electrical output (a maximized power output of 4.19 W/m2 when matched with a 0.07 MΩ resistor, a stable output current of 2.25 A/m2 and a peak Voc of 27 V). Further, a TVNG vehicle travelling intelligent sensor and system which can integrate electrical signals collected by TVNG into digital signal processing algorithms and then feed backing to the driving system, has been designed and manufactured. As an effective method for deep analysis of signals, Ensemble Empirical Mode Decomposition (EEMD) has been used for the first time for deep processing of nanogenerator signals in this work. This work provides a new model of further development of high output TVNG and a new deep signal processing methods of TVNG/TENG signal.

An unsupervised coherent receiver digital signal processing algorithm based on spectral clustering with no data preamble

AbstractA coherent optical receiver digital signal processing (DSP) scheme is proposed based on spectral clustering, which utilises spectral clustering to cluster the signals outputted by the DSP. Compared to existing blind DSP algorithms for coherent optical receivers operating at over 100Gbps with PM‐mQAM, the proposed scheme effectively suppresses various physical impairments, achieving lower bit error rates (BERs) at the same transmission distance, thus enabling longer transmission distances under the same forward error correction threshold. Furthermore, simulations of the proposed scheme on a 14GBaud PM‐16QAM coherent optical transmission system show that, at a BER of 1.9E‐2, the maximum transmission distance increases from 1700 to 2000 km, and at a BER of 3.8E‐3, it increases from 700 to 900 km.

Performance Investigation of Joint LUT and GS Algorithm at the Transceiver for Nonlinear and CD Compensation

In order to meet the increasing requirements of speed and distance, an advanced digital signal processing (DSP) algorithm is preferred without changing the system structure in intensity modulation and the direct detection (IM/DD) system. As the transmission distance increases, the power fading induced by dispersion must be mitigated. In addition, linear and nonlinear inter symbol interference (ISI) introduced by bandwidth limitation and device imperfections becomes an obstacle to achieving higher capacity. The Gerchberg–Saxton (GS) algorithm was recently used to compensate for dispersion. In this paper, GS-based pre- and post-compensation schemes in the IM/DD system with nonlinearity were investigated. We investigated and compared the performance of the GS-based pre- and post-compensation algorithm in a 28 GB aud four-level pulse amplitude modulation (PAM-4) transmission over 40 km standard single-mode fiber (SSMF). The bit error rate (BER) achieved a threshold of 3.8 × 10−3 using look-up-table (LUT), FFE, and the GS-based pre-compensation algorithm without iterations. Turning to the GS-based post-compensation scheme, 80 iterations are needed. However, the demand for FFE is reduced. The algorithm selection depends on the tolerance of the transmitter or receiver complexity in specific scenarios. The joint LUT and GS-based pre-compensation algorithm may be a preferable approach in scenarios where a low-complexity receiver is desired.

W-band photonics-aided OFDM system integrating sensing and communication with phase noise suppression scheme

Photonic-aided technology offers many advantages in millimeter-wave (MMW) communication and sensing, such as low equipment cost and wide bandwidth. The combination of photonics-aided systems with orthogonal frequency division multiplexing (OFDM) waveforms enables high-performance integration of sensing and communication. In this paper, we propose and experimentally demonstrate a W-band photonic-aided OFDM system integrating sensing and communication (ISAC). To address the destruction of signal coherence by phase noise of the system, this paper proposes an OFDM sensing scheme combined with frequency-domain filtering to reduce the sidelobe interference caused by phase noise. Combined with offline digital signal processing algorithms, the system achieves high-precision ranging-Doppler imaging with a ranging resolution of 0.96 cm at a detection distance of 2 m. In terms of communication, after 10 m of wireless transmission, the net rate reaches 47.06 Gbit/s. The proposed system makes full use of the system's resources by using OFDM signals as both the sensing and communication signals. This may be beneficial for some potential applications of 6G in the future.

Adaptive digital antenna array signal processing algorithm based on LDL decomposition

Two algorithms for inverting correlation matrices of digital antenna array signals are compared: LDL decomposition and the fringing method. The idea of comparing algorithms was to take into account the limitations on the length of the input data mantissa in the process of space-time processing using FPGAs. It has been found that rounding errors in the signal processing process in FPGAs can lead to the destruction of the directivity pattern. This is due to the fact that when implementing various algorithms for matrix inversion, the distribution of errors in the channels becomes interconnected. This means that when implementing adaptive antenna arrays on FPGAs, it is necessary to carefully choose the length of the mantissa and the conversion algorithm. In this regard, an algorithm for signal processing in an adaptive antenna array is proposed, its difference from the known ones is that when implemented on FPGAs, floating-point arithmetic of limited mantissa bit is used. When comparing two computationally efficient matrix inversion algorithms (the LDL method and the fringing method), the LDL method has higher stability. It was found that with an increase in the rank of the correlation matrix, the effect of rounding errors will be stronger. In this regard, it is necessary to determine in advance at what ratio of power sources and internal noise it is planned to use an adaptive processor.

Automated design of embedded digital signal processing systems on SOC platform

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

Design and implementation of a nano-scale high-speed multiplier for signal processing applications

Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.

DSP-based inter-channel interference monitoring in flexible wavelength-routed networks

The efficiency of optical networks employing flexible wavelength division multiplexing (WDM) can be increased by maximizing the throughput of each individual channel, provided that the position of its neighboring channel is known with sufficient accuracy in order to avoid inter-channel interference. In this paper, we propose a digital signal processing (DSP) algorithm, leveraging the use of an artificial neural network (ANN), to estimate the neighboring channels’ distance by processing raw digital samples from a standard coherent receiver. We present an efficient dataset design approach, based on Latin hypercube sampling (LHS), in order to effectively optimize and validate the algorithm under different assumptions on the optical WDM channels. We investigate the accuracy of the ANN-based DSP scheme through simulation analysis, highlighting its potential in relation to the characteristics of the optical network. Finally, we validate our approach in an experimental setup using standard commercial coherent transceivers. The experimental results show that the distance from the neighboring WDM channels can be estimated with a root mean square error of less than 1.5 GHz for a channel under test with a symbol rate of 52 GBaud.

OptiComm-GPT: a GPT-based versatile research assistant for optical fiber communication systems

With the increasing capacity and complexity of optical fiber communication systems, both academic and industrial requirements for the essential tasks of transmission systems simulation, digital signal processing (DSP) algorithms verification, system performance evaluation, and quality of transmission (QoT) optimization are becoming significantly important. However, due to the intricate and nonlinear nature of optical fiber communication systems, these tasks are generally implemented in a divide-and-conquer manner, which necessitates a profound level of expertise and proficiency in software programming from researchers or engineers. To lower this threshold and facilitate professional research easy-to-start, a GPT-based versatile research assistant named OptiComm-GPT is proposed for optical fiber communication systems, which flexibly and automatically performs system simulation, DSP algorithms verification, performance evaluation, and QoT optimization with only natural language. To enhance OptiComm-GPT’s abilities for complex tasks in optical fiber communications and improve the accuracy of generated results, a domain information base containing rich domain knowledge, tools, and data as well as the comprehensive prompt engineering with well-crafted prompt elements, techniques, and examples is established and performs under a LangChain-based framework. The performance of OptiComm-GPT is evaluated in multiple simulation, verification, evaluation, and optimization tasks, and the generated results show that OptiComm-GPT can effectively comprehend the user’s intent, accurately extract system parameters from the user’s request, and intelligently invoke domain resources to solve these complex tasks simultaneously. Moreover, the statistical results, typical errors, and running time of OptiComm-GPT are also investigated to illustrate its practical reliability, potential limitations, and further improvements.

Alamouti-coded DSP algorithm with a simplified PTBC decoder for next-generation optical access networks

The use of Alamouti-coded polarization-time block code (A-PTBC) in combination with a simple single polarization coherent receiver enables phase-diverse coherent detection without any optical polarization tracking. However, applying this technique to high-speed single-carrier systems is not straightforward, as it requires specialized digital signal processing (DSP) algorithms for data recovery, which increases DSP complexity. In this paper, we propose a novel Alamouti-coded coherent algorithm designed to significantly reduce the complexity of the receiver DSP for data recovery. The proposed algorithm achieves the comparable performance to the conventional algorithm but requires only half the number of necessary equalizers for data recovery. We validate its performance through simulations and also experimentally demonstrate a 100 Gb/s 16-quadrature amplitude modulation (QAM) single-carrier coherent system employed the single-polarization coherent receiver over 20 km of standard single-mode fiber (SMF). Through the performance verification, the coherent system with the proposed algorithm exhibits performance comparable to that of the conventional Alamouti-coded coherent system and achieves a power budget of 34 dB when the transmit launch power is set to 7 dBm at a Bit Error Rate (BER) of 1 × 10−2 for 0-20 km fiber transmission.

Разработка и исследование подхода к обработке сигналов цифровых измерительных трансформаторов тока и напряжения

During the development of secondary systems of stations and substations, including relay protection, automation, control, electricity metering, etc., qualitative changes have recently occurred due to the introduction of digital technologies. The introduction of digital technologies is supported by innovative development programs such as “Digital Transformation 2030”. The introduction of digital technologies is associated with the use of digital data transmission channels according to uniform standards. Projects of “digital substations” are being actively implemented with the transmission of digital information at all levels, including the primary equipment, the transmission of information both from current and voltage measuring transformers, and from switching devices. Currently, digital instrument transformers are actively being developed and implemented, in which information about measured currents and voltages is presented in digital code. New approaches to measure primary currents and voltages, and transmit information pose new challenges, and open prospects for improving signal processing methods used for relay protection purposes. Thus, the relevant aim of the study is the development and research of approaches to digital processing of signals of digital instrument current and voltage transformers. To solve the problems posed within the framework of this study, analytical and numerical solution methods have been used. Numerical methods are applied using software products such as MathCAD and the Python programming language to generate signals and display them on graphs. To substantiate the reliability, verification of the results obtained by different methods is carried out. The authors have formulated an approach to digital processing of signals obtained using current sensors of a digital instrument transformer. The authors have studied the approach to determine synchronized current vector values by processing information received from primary current converters. The characteristics of the algorithm for obtaining a vector have been analyzed and the dependences of errors on the influence of distorting factors have been plotted. The proposed approach is a development of the existing approach to obtain a vector by getting information from current sensors operating on different physical principles. The results show the advantages of the proposed method. The proposed digital signal processing algorithm is more technically expensive since it contains at least two metrologically calibrated measuring channels instead of one. However, all other things being equal, it allows to increase the accuracy and speed of the digital processing algorithms taken as a prototype. The results obtained can be used to formulate algorithms for measuring relay protection devices.

LUAEMA: A Loop Unrolling Approach Extending Memory Accessing for Vector Very-Long-Instruction-Word Digital Signal Processor with Multiple Register Files

Loop unrolling can provide more instruction-level parallelism opportunities for code and enables a greater range of instruction pipeline scheduling. In high-performance very-long-instruction-word (VLIW) digital signal processors (DSPs), there are special registers to address. To further improve the instruction-level parallelism of code for such DSPs by making full use of these registers, in this paper, we propose a more effective loop unrolling approach through extending memory accessing (LUAEMA). In this approach, the final unrolling factor is computed by a model in which every register kind and every memory accessing operation are considered. For basic digital signal processing algorithms, the unrolling factor under the LUAEMA is larger than that under the conventional loop unrolling approach. We also provide the opportunity to reduce the number of instructions in a loop during the code transformation of loop unrolling. The experimental results show that the loop unrolling approach proposed in this paper can achieve an average speedup ratio ranging from 1.14 to 1.81 compared with the conventional loop unrolling approach. For some algorithms, the peak speedup ratio is up to 2.11.

Design of Intelligent Control Systems for Layered Water Injections in Oilfields

With rapid socio-economic growth and increased energy demand, exploration and exploitation of oil and gas resources have become crucial. Long-term exploitation leads to problems such as pressure drop and production reduction in oil fields, and water injection technology has become a common method to improve these problems. The traditional direct water injection for oil extraction has problems such as high injection cost and low oil recovery efficiency. Therefore, an intelligent control system for different oilfield reservoirs is needed. This study focuses on the layered water injection intelligent system based on advanced sensor technology, digital signal processing and intelligent algorithms. The article reviews the advantages of layered water injection system and the current research status, designs an intelligent control structure including hardware circuits and modular software processes, and adopts adaptive particle swarm optimization algorithm as the core of intelligent control.

THE DESIGN OF THE PIPELINED RISC-V PROCESSOR WITH THE HARDWARE COPROCESSOR OF DIGITAL SIGNAL PROCESSING

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.
 In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.
 Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.
 Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.
 Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.
 Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

Optimizing parametric acoustic arrays for high-fidelity low-frequency signals

Parametric acoustic array (PAA) can leverage the nonlinear behavior of sound travelling through the nonlinear medium (e.g., air, water, human tissues) to generate low-frequency broadband high-directivity sound due to the self-demodulation of finite-amplitude modulated ultrasonic waves. However, while propagating, self-demodulated signals (hereon message) interact one with another, leading to message deformation and increase of the total harmonic distortion (THD). This makes it problematic to use powerful PAA to control complex low-frequency signals. This work explores a method for reducing THD by optimizing the input signal using various digital signal processing algorithms. The sustainability of the required spectral components with distance and the spatial boundaries of the operation of the proposed optimization algorithm are also investigated experimentally with a 520-channel hexagonal PAA and numerically. The simulations were done via k-wave acoustic toolbox considering nonlinearities and power law absorption.

Improving Utilization of Dataflow Unit for Multi-Batch Processing

Dataflow architectures can achieve much better performance and higher efficiency than general-purpose core, approaching the performance of a specialized design while retaining programmability. However, advanced application scenarios place higher demands on the hardware in terms of cross-domain and multi-batch processing. In this article, we propose a unified scale-vector architecture that can work in multiple modes and adapt to diverse algorithms and requirements efficiently. First, a novel reconfigurable interconnection structure is proposed, which can organize execution units into different cluster typologies as a way to accommodate different data-level parallelism. Second, we decouple threads within each DFG node into consecutive pipeline stages and provide architectural support. By time-multiplexing during these stages, dataflow hardware can achieve much higher utilization and performance. In addition, the task-based program model can also exploit multi-level parallelism and deploy applications efficiently. Evaluated in a wide range of benchmarks, including digital signal processing algorithms, CNNs, and scientific computing algorithms, our design attains up to 11.95× energy efficiency (performance-per-watt) improvement over GPU (V100), and 2.01× energy efficiency improvement over state-of-the-art dataflow architectures.

Low-complexity and low-latency equalization technique - probabilistic noise cancellation.

Both inside data centers (DCs) and in short optical links between data centers (DC campuses), intensity-modulation and direct-detection (IMDD) systems using four-level pulse amplitude modulation (PAM4) will dominate this decade due to low transceiver price and power consumption. The next DC transceiver generation based on 100 Gbaud PAM4 will require advanced digital signal processing (DSP) algorithms and more powerful forward error correction (FEC) codes. Because of bandwidth limitations, the conventional DC DSP based on a few-tap linear feed-forward equalizer (FFE) is likely to be upgraded to more complex but still low-complexity Volterra equalizers followed by a noise whitening filter and either a maximum likelihood sequence estimation (MLSE) or a maximum a posteriori probability (MAP) algorithm. However, stringent power consumption and latency requirements may limit the use of complex algorithms such as decision feedback equalizer (DFE) or MLSE/MAP in DC networks (DCN). In this paper, we introduce a low-complexity, low-latency algorithm based on a feedforward structure, yielding a performance between DFE and MLSE. We call the novel equalization algorithm probabilistic noise cancellation (PNC), since it weights noise patterns based on their probabilities in the presence of bandwidth limitations. The probabilistic weighting is efficiently exploited in correcting correlated errors caused by noise coloring in the FFE.

High key rate continuous-variable quantum key distribution using telecom optical components

Quantum key distribution (QKD) is one quantum technology that can provide secure encryption keys for data transmission. The secret key rate (SKR) is a core performance indicator in QKD, which directly determines the transmission rate of enciphered data. Here, for the first time, we demonstrate a high-key-rate Gaussian-modulated continuous-variable QKD (CV-QKD) using telecom optical components. The framework of CV-QKD over these components is constructed. Specifically, the high-rate low-noise Gaussian modulation of coherent states is realized by a classical optical IQ modulator. High-baud low-intensity quantum signals are received by an integrated coherent receiver under the shot-noise limit. A series of digital signal processing algorithms are proposed to achieve accurate signal recovery and key distillation. The system can yield a high asymptotic SKR of 10.37 Mbps within 20 km standard telecom fiber, and the secure distance can exceed 100 km. This result confirms the feasibility of CV-QKD with state-of-the-art performance using telecom optical components. Besides, due to the ease of integrating these discrete components, it provides a high-performance and miniaturized QKD solution for the metropolitan quantum network.

Optical access networks for fixed and mobile applications [Invited Tutorial

Optical access networks are playing a more critical role in providing diverse emerging applications for human- and machine-type communications. With the ever-growing demand for higher capacity, higher fidelity, and massive connections, numerous innovative transmission schemes and digital signal processing algorithms have been proposed in a cost-effective way. Here, we focus on two main scenarios, namely, fixed and mobile access. For the fixed access network, the solutions are categorized into direct detection, simplified coherent detection, and self-coherent detection. For the mobile fronthaul, we classify the schemes according to the functional split, including the analog radio-over-fiber, common public radio interface (CPRI), enhanced CPRI (eCPRI), and integrated and hybrid digital/analog-over-fiber interfaces. This tutorial provides an overview of the enabling technologies for fixed and mobile applications in the fifth-generation (5G) era and beyond.