Real-time Digital Signal Processing Research Articles

Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications

As technology advances at a rapid pace, there is an increasing need for real-time digital signal processing (DSP) applications that are efficient and swift. DSPs, or digital signal processors, are crucial components of several engineering disciplines. For processes like convolution and Fourier transforms in DSPs, rapid multiplication is essential. Multiplication is one of the basic mathematical operations used by all applications. Many different multiplier designs have been developed to boost their speed. When compared to array and booth multipliers—the products of decades of hard research—vedic multipliers are among the fastest and lowest power multipliers. The sixteen sutras, or algorithms, that the Vedic Multiplier uses are primarily logical procedures. They are the fastest and most effective because several of them have been proposed using the Urdhava Tiryakbhyam sutra. The purpose of this study is to provide an overview of the numerous biomedical applications of Vedic Multiplier in the wide field of digital signal processing, including denoising of Electrocardiogram (ECG) and Electroencephalogram ( EEG) signal. Particular attention is paid to how current Vedic Multiplier designs have been altered to increase speed and performance metrics.

Performance Analysis of Vedic Multiplier in Signal Processing Applications

The demand for quick and effective real-time digital signal processing (DSP) applications has increased due to the rapidly advancing technology. Digital signal processors, or DSPs, are essential to several engi- neering specialties. In DSPs, quick multiplication is crucial for operations like Fourier transformations and convolution. One of the fundamental arithmetic processes required by all applications is multiplication. To increase their speed, numerous multiplier designs have been created. Vedic multipliers are among the quick- est and lowest power multipliers compared to array and booth multipliers which are the result of decades of intensive research. The Vedic Multiplier works with sixteen sutras, or algorithms, most of which are for logical processes. Since several of them have been proposed utilizing the Urdhava Tiryakbhyam sutra, they are the fastest and most efficient. This paper's goal is to summarise the many uses of Vedic Multiplier in the broad field of digital signal processing such as image processing, with a focus on the various ways that Vedic Multiplier designs that are now in use have been modified to improve speed and performance metrics.

Designing and Validating Magnetic Motion Sensing Approaches with a Real-time Simulation Pipeline

Abstract Magnetic motion sensing enables non-contact tracking of relative position and orientation in 3D space. With recent advances in sensor and actuator devices, applications in human movement analysis seem feasible. However, establishing a setup from scratch in terms of hardware and software is challenging. Therefore, we introduce a comprehensive simulation pipeline based on a digital twin concept that enables the design and validation of new approaches based on kinematics, magnetics, and digital real-time signal processing. We also elaborate on related applications.

Programmable resonant and forced mode high-voltage RF generator for dielectric barrier discharge and quadrupole mass filter

Dielectric barrier discharge, originally called silent discharge, is the electrical discharge between two electrodes separated by an insulating dielectric barrier. A high-voltage alternating current is required to generate the discharge process. There are two major principles of operation to implement a high-voltage generator: resonant mode and forced mode. While operating in forced mode, the working frequency is forced by the user using internal electronic devices. On the other hand, in resonant mode, the operating frequency is determined by the resonant circuit, which includes the external capacitance, inductance, and resistance of the load. This work shows a flexible circuit based on a real-time digital signal processor and a full H-bridge that combines the two topologies and can be used as a controller for dielectric barrier discharge and a quadrupole mass filter with varying capacitance.

Traveling Wave-Based Primary Protection and Fault Localization Scheme for MTDC Grid Considering IEC 61869-9 Measurement Standard

Traveling wave (TW) based protection and fault localization requires high sampling frequency measurements (500 kHz - 1 MHz) and are non-compliant to the IEC 61869-9 measurement standards, which allows maximum sampling frequency of 96 kHz for DC application. This work proposes a novel low sampling frequency (50 kHz) TW based primary protection and real-time DC fault localization technique for multi terminal high voltage DC (MTDC) grid which is compliant with the aforementioned measurement standard. In the proposed MTDC protection scheme, a TW arrival time (TWAT) is estimated under low sampling frequency measurement using cascaded combination of modified mathematical morphology gradient (MMG), sobel operator and linear regression tool. Subsequently, the TWAT information at both DC link terminals is communicated via dedicated communication channel compliant to IEC-61850-9-2 standard. And if the TWAT difference between DC terminals is less than the TW propagation threshold for the protected DC line, then a DC trip signal is issued to the associated hybrid DC circuit breaker (HDCCB). For fast power system restoration, the same TWAT information is also used for real-time fault localization in the faulted DC line, which is also compliant with IEC 61869-9 measurement standards. Finally, the practical feasibility of the proposed algorithm is demonstrated through control hardware-in-loop testing with real-time digital simulation setup and TI TMS320F28379d digital signal processor card.

Physics-Based LED Modeling and Nonlinear Distortion Mitigating With Real-Time Implementation

In this paper, a nonlinear model for Light Emitting Diodes (LEDs) inspired by semiconductor physics, and a corresponding post-compensator are implemented in a Field Programmable Gate Array (FPGA) for real-time Visible Light Communications (VLC). Our experiments demonstrate that the LED model effectively characterizes the dynamic LED nonlinearity, including the memory effects. The output signal of this nonlinear LED model shows a good resemblance with the measured LED output. In addition, a dedicated nonlinear equalizer, say, a post-compensator, inspired by this LED physical model can mitigate the nonlinear distortion substantially. Thereby it facilitates high data rate over the bandwidth-limited LED. It shows that the nonlinear compensator is attractive for practical real-time digital signal processing systems due to its high performance and low complexity.

Real-time digital signal processing implementation for in-beam PET of radiotherapy imaging in HIMM

The in-beam positron emission tomography (ibPET) is dedicated to radiotherapy imaging of the heavy-ion medical machine (HIMM), which requires precise online measurement, as well as real-time signal processing capability of the electronics. In this paper, we present the implementation of real-time digital signal processing in the data acquisition unit (DAQU) for an ibPET system based on the photomultiplier tube (PMT) readout of lutetium-yttrium oxyorthosilicate (LYSO) scintillator crystals. We have designed 10-channel customized signal processing circuit on a high-performance FPGA, which supports 3 working modes (single event processing mode, self-calibration mode and raw ADC data mode), position calculation, crystal locating, event sorting, and etc. Moreover, the implementation of real-time corrections is capable of dealing with photon peak correction to 511 keV and crystal ID-based time correction. The implemented real-time ibPET system can achieve 46% data compression and beyond 1,000,000 events/sec/channel signal processing capabilities. A series of initial tests is conducted, and the results indicate that this design meets the application requirement on online processing.

FPGA-based electronic system for the control and readout of superconducting quantum processors.

Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.

Real-time reception of NHS-OFDM signal with SPA-enhanced channel estimation for intensity-modulated direct-detection systems

In this Letter, we have experimentally verified a low-complexity subcarrier pairwise-averaging (SPA)-enhanced channel estimation (CE) method for small-size fast Fourier transform (FFT) non-Hermitian symmetric orthogonal frequency-division multiplexing (NHS-OFDM) transceivers. Compared with intra-symbol frequency averaging (ISFA), more than 20% look-up tables and 10% logic power consumption can be saved. The least-square (LS), ISFA, and SPA CE methods are compared by offline and real-time digital signal processing approaches. The results show that the receiver sensitivity of the SPA NHS-OFDM transmission system with 64/128-point FFT can be improved by more than 1 dB at the bit error rate of 3.8 × 10-3 compared to the LS.

An Introduction to High Sample Rate Nyquist Analog-to-Digital Converters

Increasingly wider band analog signals found in multiple information and communication technology applications, requiring real-time digital signal processing, demand analog-to-digital converters with ever higher sample rate. Several innovative techniques, from the circuit level, to architecture and algorithms, have enabled remarkable breakthroughs in a relatively short span of time. This overview article aims to introduce this topic and to point to some of the most notable results, while also highlighting open problems and engineering trends.

Hardware-efficient generation and reception of NHS-OFDM signal for direct-detection PON

Orthogonal frequency-division multiplexing-based passive optical network (OFDM-PON) with low-cost direct detection is the current research focuses of access networks. It can realize multi-dimensional bandwidth allocation based on subcarriers and time slots. In general, the inverse fast Fourier transform (IFFT) with Hermitian symmetric (HS) mapped symbols is applied to generate the real-valued baseband signal for intensity modulation. However, only half of the subcarriers can be employed to carry user data, while the other half are modulated by the corresponding conjugate data. Therefore, both IFFT and FFT are not fully utilized in HS-OFDM systems. Under the same bandwidth granularity (data subcarriers) and data transmission rate, the non-HS OFDM (NHS-OFDM) can reduce IFFT/FFT size by half. The hardware implementation and power consumption will be significantly reduced compared to the HS-OFDM. In this paper, we design and implement the baseband HS/NHS-OFDM transceivers based on field programmable gate array chips and data converters. On-chip resource usage and power consumption are analyzed and compared. It shows that the NHS-OFDM transmitter (receiver) can save up to 58% (58%) multipliers, 46.8% (41.7%) registers, and 48% (42.9%) look-up tables. About 11.9% (19.6%) of on-chip power consumption is reduced for the transmitter (receiver). In addition, the two real-time baseband transceivers are comparatively investigated in a directly-modulated laser-based direct detection transmission system. The bit error rate (BER) performance after 20 km standard single-mode fiber transmission is measured with both offline and real-time digital signal processing (DSP) algorithms. It exhibits that the NHS-OFDM system’s power penalty is negligible at the BER of 3.8e−3, compared to the HS-OFDM. Moreover, the real-time receivers have a similar BER performance to corresponding offline ones.

A general-purpose pipeline to interface the Tympan hardware with an external computer

Some audio applications require resource-heavy algorithms which cannot be run on real-time digital signal processors such as the Tympan hardware directly due to memory and processing constraints. These algorithms can, however, run on an external computer (PC), and their outcomes can be relayed back to the Tympan where necessary adjustments can be made in the audio processing elements of the underlying hardware. The proposed pipeline includes a 4-channel audio input, the algorithm running on the PC, the Tympan hardware, and a 4-channel output. The Tympan hardware acquires input audio from the Tympan’s onboard and/or external microphones with the I2S protocol. The input data are transmitted to the algorithm running on the external PC via USB/Serial communication by exposing the Tympan as a soundcard interface. The output of the PC algorithm is then sent back to the Tympan, through serial communication, so that the underlying audio processing parameters are adjusted. A possible use case is also discussed: a detection algorithm runs on the PC and serial commands are sent back to Tympan to alter the audio outputs, e.g., by playing masking noise. The pipeline is built such that each element can be used independently, abstracting the interconnection of the pipeline elements.

A Novel Dentary Bone Conduction Device Equipped with Laser Communication in DSP.

In this study, we designed a dentary bone conduction system that transmits and receives audio by laser. The main objective of this research was to propose a complete hardware design method, including a laser audio transmitter and receiver and digital signal processor (DSP) based digital signal processing system. We also present a digital filter algorithm that can run on a DSP in real time. This experiment used the CMU ARCTIC databases’ human-voice reading audio as the standard audio. We used a piezoelectric sensor to measure the vibration signal of the bone conduction transducer (BCT) and separately calculated the signal-to-noise ratio (SNR) of the digitally filtered audio output and the unfiltered audio output using DSP. The SNR of the former was twice that of the latter, and the BCT output quality significantly improved. From the results, we can conclude that the dentary bone conduction system integrated with a DSP digital filter enhances sound quality.

Design of High-Speed Low Power Computational Blocks for DSP Processors

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

Parallel-Connected Buck–Boost Converter with FLC for Hybrid Energy System

The control of renewable energy sources is more complicated when used as hybrid energy systems. Power electronic circuits are used to convert and store the electrical energy generated from renewable energy sources. However, the high frequency switching in these power electronic circuits complicates the control of the systems. Advanced control methods are required to control such complex systems. In this study, a hybrid energy system was devised and implemented experimentally to first convert the solar and wind energy to electrical energy and, then to store and use it through a common bus voltage. The study focused on buck–boost converters' parallel connection and deviations from the common bus voltage level were taken into account. The converter system's control was tested with FLC as the best solution, and the results obtained from simulation and experiments were compared. The experimental setup was controlled with a fast and real-time digital signal processor (DSP). Current and voltage measurement circuits, MOSFET drivers, and parallel-connected buck–boost converters were realized experimentally. The simulations and experimental results were suitable for various solar and wind conditions. This hybrid system was also tested at low solar radiation and at low wind speeds to stabilize common bus voltage and energy harvesting.

Symmetric 10 Gbit/s 40-km reach DSP-based TDM-PON with a power budget over 50 dB.

This paper introduces the concept of a symmetric 10 Gbit/s high power-budget TDM-PON based on digital coherent technology and confirms its feasibility through a bidirectional transmission experiment with a transmission distance of 40 km and power budget of more than 50 dB. Burst-mode upstream 10 Gbit/s binary-phase-shift-keying (BPSK) signals synchronized by the clock recovered from downstream 10 Gbit/s NRZ signals are detected by using an optical pre-amplifier and coherent detection based on real-time burst-mode digital signal processing (DSP) in the optical line terminal (OLT). The real-time DSP implements coefficient handover in the adaptive equalizer to allow the reception of burst-mode upstream BPSK signals with short preamble length. An experimental bit error performance evaluation of the real-time burst-mode DSP yields the receiver sensitivity of -45.1 dBm for upstream burst-mode BPSK with a preamble length of 1.3 μs. For downstream signals, the receiver sensitivity of -38.9 dBm is achieved by using a chirp-controlled transmitter with optical post-amplifier so as to avoid the signal distortion created by the chromatic dispersion of single mode fiber (SMF) when the launched power is increased.

Feature extraction of milling chatter based on optimized variational mode decomposition and multi-scale permutation entropy

In the milling process, chatter is easy to occur and has a very adverse impact on the quality of the workpiece and the production efficiency. A chatter feature extraction method based on optimized variational mode decomposition (OVMD) and multi-scale permutation entropy (MPE) was proposed to solve the problem that it is difficult to detect the machining chatter state during milling. The methodology presented in this article allows the occurrence of machining chatter to be effectively identified through real-time digital signal processing and analysis. First, in order to solve the problem of variational mode decomposition (VMD) parameter selection, an automatic selection method based on particle swarm optimization (PSO) and the maximum crest factor of the envelope spectrum (CE) was proposed. Then, the decomposed signal was reconstructed based on the energy ratio. In order to solve the problem that the single-scale permutation entropy (PE) cannot detect milling chatter well, the MPE was introduced to detect milling chatter. Finally, experimental verification was carried out, and the MPE of the reconstructed signals at different scales was extracted and analyzed. The results show that using the OVMD algorithm to process the signals can significantly improve the discrimination of MPE. With the increase of the scale factor, the MPE of the milling signals tends to decrease. At the same time, MPE is better than single-scale PE in chatter detection, and the MPE at scale factor of 4 is more conducive to chatter detection.

Flows of Inhomogeneous Matter: Improvising an augmented violin

This article reflects on how personal digital musical instruments evolve and presents an augmented violin developed and performed by the author in improvised performance as an example. Informed by the materialism of Gilles Deleuze and Felix Guattari, an image of ‘flows of inhomogeneous matter’ provokes reflection on a mode of production common to artisanal craftmanship and digital lutherie alike, namely the pre-reflective skilfulness negotiating the singularities of inhomogeneous matter with the demands of the production – a process which itself may be thought of asim-pro-visation(‘un-fore-seen’). According to Gilbert Simondon, all technical objects develop in this way: functional interdependency emerges when abstractly ideated elements begin to enter into unanticipated synergistic relationships, suggesting a material logic dependent on unforeseen potentialities. The historical development of the acoustic violin exemplifies such an evolution, with, like all technical objects, additional latent potential. Digital artists can work like artisanal craftsmen in tinkering with technical elements, teasing out their synergies through abductive, trial-and-error experimentation. In the context of developing digital musical instruments, model-free design of real-time digital signal processing symmetrising action and perception yields highly refined results. Like musical improvisation – constrained by time – improvised development of these instruments turns the material obstacles into their very means of realisation.

Выпрямление и детектирование сигналов в NI ELVIS комплексе

A half-wave diode rectifier is represented as a nonlinear circuit to study in a laboratory course of electrical engineering. The control and measurement complex NI ELVIS effectively displays the nonlinear circuit properties using oscillograms and spectrograms of signals. The coefficients of ripples and nonlinear distortions are calculated. They help to evaluate the influence of the circuit parameters on the quality of signal conversion when rectifying and detecting. The advantages of the NI ELVIS complex consist in, for instance, the real-time digital signal processing, the visualization of results, the ergonomic visualization tools. These advantages provide clarity and precision in the presentation of complex nonlinear processes in electrical engineering.

Distributed Cooperative Relaying Based on Space-Time Block Code: System Description and Measurement Campaign

In cooperative relaying, intermediate stations are required to enhance the end-to-end transmission performance. The performance of the cooperative relaying scheme has been investigated theoretically and via computer simulations. However, cooperative relaying using transmit diversity techniques in actual environments has not been investigated thus far. This paper presents an experimental system for distributed cooperative relaying using space-time block code and evaluations of its transmission performances in real propagation channels. To this end, four wireless stations—specifically, one source, two relays, and one destination—were developed using analog transceivers and field-programmable gate arrays for real-time digital signal processing. Sample timing and frequency synchronizations among the four wireless stations were established by using the received signals as a reference. The end-to-end error performance of distributed cooperative relaying was compared to those of noncooperative relaying schemes, and the performances of three relaying schemes were evaluated quasisimultaneously in terms of their cumulative distribution functions of the bit-error ratios (BERs). The experimental results indicated that the BER performance of the two-hop distributed cooperative relaying scheme was substantially superior to those of noncooperative two-hop relaying schemes, including a route diversity scheme.