Digital Polar Transmitter Research Articles

A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS

This article presents a fully integrated digital polar transmitter (DPTX) incorporating an efficiency-enhanced digital power amplifier (DPA) and a high-resolution digital-to-time converter (DTC). The proposed single-ended Doherty (SED) PA topology with switched-capacitor (SC) arrays can generate four power efficiency peaks that significantly improve the power-added efficiency (PAE) at the power amplifier (PA)’s power back-offs (PBOs). In addition, this work utilizes a three-segment DTC, built with a delay-locked loop (DLL), to improve the phase resolution and enable real-time process-voltage-temperature (PVT) calibration of the DTC. Fabricated in a 28 nm CMOS technology, the DPTX achieves a peak output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{out}})$</tex-math> </inline-formula> of 27.7 dBm and a peak PAE of 33.4% at a 2.1 GHz carrier frequency. The PAEs at 2.5, 6, and 12 dB PBOs are 31.1%, 24.5%, and 18%, respectively. With the 2.1 GHz carrier, the DTC achieves 360 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> full output phase range, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> differential nonlinearity (DNL), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> integral nonlinearity (INL), and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 133.86 dBc/Hz phase noise at a frequency offset of 1 MHz, while the power dissipation is only 14 mW. When testing the 10 MHz (and 20 MHz) long term evolution (LTE) 64 QAM signals with a 6.2 (5.0) dB peak-to-average power ratio (PAPR), the DPTX achieves an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{out}}$</tex-math> </inline-formula> of 21.5 (22.7) dBm, an average PAE of 23.5% (24.6%), an average system efficiency (SE) of 22.5% (23.8%)–, 30.6 (–27.7) dB error vector magnitude (EVM), and –34.2/–32.6 (–30.1/–29.2) dBc adjacent channel leakage ratio (ACLR). Note that these results have been achieved with only the on-chip digital pre-distortion (DPD) algorithm.

Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis

Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis

A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS

This work presents a wideband digital polar transmitter (DPTX) with an integrated capacitor-digital-to-analog converter (C-DAC)-based digital-to-phase converter (DPC). A normalized CORDIC algorithm is introduced to convert the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> baseband signals to a constant envelope to overcome the PM bandwidth expansion issue and avoid the amplitude modulation (AM)–phase modulation (PM) nonlinearity. In the DPC, the switched-capacitor DAC topology is employed for good linearity, and the eight-phase cell-reused technique is proposed to reduce the power consumption and increase the phase amplitude. Besides, the harmonic rejection technique is introduced to remove the third-/fifth-order and higher order local oscillator (LO) harmonics to maintain phase linearity. A broadband switched-transformer digital power amplifier (DPA) is adopted in this proposed DPTX for 0–18-dB deep power back-off efficiency enhancement. Implemented in 40nm CMOS, the DPTX is powered by only one 1.1-V supply and occupies a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4 \times 1.4$ </tex-math></inline-formula> mm2 die area. The DPC achieves the maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of ±1°/±0.8° and 12.7-mW power consumption at 1.5 GHz. The DPTX realizes wideband frequency coverage of 1.2–2.5 GHz with only 0.7-dB power variations. The DPTX achieves 20.1-dBm peak output power with 23.7% system efficiency at 1.5 GHz. With a 10-MHz 64-quadrature amplitude modulation (QAM) LTE signal, the DPTX achieves 15.0 dBm average output power, 15.2% system efficiency, and an error vector magnitude (EVM) of −28.6 dB at 1.5 GHz.

A Sub-GHz multimode digital polar transmitter for 802.11ah and NB-IoT applications

This paper presents a sub-GHz multimode efficiency-enhanced digital polar transmitter for IoT applications. The Class-G technique and wideband matching network are introduced in the switched-capacitor digital power amplifier (DPA) to enhance the 6 dB back-off efficiency and achieve 550–950 MHz wide frequency coverage. The digital baseband processing module is flexibly reconfigurable to support both 802.11ah and NB-IoT protocols. Moreover, the canonic signed digit (CSD) coding and first-order hold (FOH) interpolation techniques are employed to reduce power consumption. Implemented in 55 nm CMOS technology, this digital transmitter (DTX) achieves 23.7dBm peak power, 44.6% peak PAE and 36.1% PAE at 6 dB power back-off at 800 MHz. The DTX obtains 16.7dBm average output power, 33.9% average PAE with −28.8 dB EVM for the 2 MHz 64QAM 802.11ah signal, and 18.6dBm average output power, 37.5% average PAE with −19.8 dB EVM for the 12-subcarrier 180 kHz NB-IoT signal.

Quantized Polar Transmitters for Power Efficient Massive MIMO Systems

This letter investigates the feasibility of the quantized digital polar transmitter architecture in a downlink multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) system, where a low amplitude resolution and a moderate phase resolution are utilized. We derive a lower bound on the average sum-rate achievable with Gaussian signaling inputs and linear precoding by a simple diagonal approximation for the quantization distortion. The analysis and simulations demonstrate that the quantized polar transmitter can enable excellent performance in terms of average sum-rate throughput, symbol error rate (SER), and out-of-band (OOB) emission level, thus providing an attractive option for the traditional Cartesian architecture.

Analysis of Spectral Degradation and Error Compensation in 5G NR Digital Polar Transmitters

Cellular standards evolve to support increasingly higher bandwidths which results in strict in- and out-of-band requirements such as lower error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Digital polar transmitters, which are showing the best performance in terms of power consumption, are challenged to fulfill these requirements. This work will show that even in case of ideal analog components and infinite digital resources, there are principle limitations in terms of out-of-band noise for digital polar transmitters. A typical polar modulation will be compared to a theoretical signal with continuous amplitude modulation. The analysis of the resulting error signal suggests a decomposition into two components which can be partially compensated in the amplitude and phase modulation paths. Based on that decomposition a compensation algorithm has been developed and evaluated with a 400 MHz 5G New Radio (NR) signal for Band n257 on Frequency Range 2 with carrier frequency of 26.5 GHz. The compensation results in an out-of-band noise reduction of 44 dB close to the carrier frequency. Furthermore, EVM improvements for NR signals are demonstrated.

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) for wide-channel phase modulation with multiband support. DTC-based phase modulation enables high-efficiency polar operation with high-efficiency RFDAC. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with a limited DCO tuning range of only 7.3–8.7 GHz (±8.7%). Phase modulation of narrowband signals (e.g., one resource block) using DTC could result in spurs in output spectrum due to the almost periodic nature of DTC errors. A theoretical analysis is presented that predicts the location of these spurs and a technique to eliminate such spurs by appropriately adjusting the PLL frequency is introduced. A new digitally controlled-edge-interpolator architecture is also presented to minimize dynamic errors, which is necessary in order to meet stringent cellular noise requirements. The DTC was implemented using digital synthesis and auto-place-and-route (APR) tools, requiring very limited analog layout resources. The TX was fabricated in 14-nm FinFET and it achieved a noise of −153/−150 dBc/Hz for LTE5/LTE20 in Band1 at +4-dBm output power with DTC power dissipation of 27 mW.

A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO

The unlicensed 57–71-GHz wireless spectrum offers high throughput and scalable personal area connectivity. To implement high-speed energy-efficient signaling, we present a power back-off-efficient digital polar transmitter (TX) supporting multi-gigasymbol per second switching rates and higher order modulations up to orthogonal frequency-division multiplexing (OFDM) 64-QAM. Pulse shaping of the direct digitally modulated waveform outputs for spectral filtering is achieved in low power with a low oversampling ratio and analog filtering. Channel bonding and selection is supported with a frequency configurable local oscillator (LO) chain. Multiple-input multiple-output (MIMO) is implemented with low area overhead using a differential dual-polarization (DP) printed circuit board (PCB) antenna supporting simultaneous vertical/horizontal (V/H)-polarization data streams and high cross-polarization (X-pol) isolation. The 0.9-V 28-nm CMOS TX prototype with polarization MIMO achieves up to 42-Gb/s throughput at 4.3-pJ/b efficiency and 12 b/symbol of OFDM/single-carrier (SC) signaling.

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153 dBc/Hz Noise in 14-nm FinFET

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) to enable high-efficiency polar RFDAC for multiband and wide-channel applications. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with DCO tuning range of only 7.3-8.7 GHz (±8.7%). The TX was fabricated in 14-nm FinFET and achieves noise of -153/-150 dBc/Hz for LTE5/LTE20 in Band1 with DTC power dissipation of 27 mW. The DTC was implemented using digital Automatic-Place-and-Route tools, requiring very limited analog layout resources.

A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signal bandwidth, and a fractional-N frequency synthesizer. Passive current mixer is employed in the receiver to improve the linearity and avoid the sensitivity degradation due to 1/ ${f}$ noise. Automatic I/Q imbalance calibration is integrated to improve image rejection ratio (IRR) with the aid of external FPGA. The transmitter is implemented in the digital polar architecture to improve the narrow-band spectrum purity, integrated with an inverse Class-D digital power amplifier (DPA) to achieve high output power and efficiency. A Class-C voltage-controlled oscillator with automatic frequency control assisted the dynamic gate biasing technique is used in the fractional-N PLL frequency synthesizer. Two prototypes are implemented in 180-nm CMOS. By optimizing analog baseband configuration in the receiver and utilizing the revised thermometer-coding and binary-coding-based array placement in the DPA, the receiver achieves 4.0-dB noise figure, 48-dB IRR, and 60-dB PGA dynamic range, and the DPA outputs 23.2dBm maximum saturation power with 44.5% PAE. Furthermore, the transmitter system verifications demonstrate 3.87% error-vector magnitude (EVM) for 891 MHz $\pi $ /4-DQPSK signals at 18.87-dBm output power with −40-dBc out-of-band rejection. The transmitter achieves a dynamic range from −35 to 20 dBm when the demodulation EVM threshold of the system is set to 10%.

A Digital Polar Transmitter With DC–DC Converter Supporting 256-QAM WLAN and 40-MHz LTE-A Carrier Aggregation

A digital polar transmitter is introduced using 9-b thermometer-coded uniform cells for wideband signal. By analyzing amplitude and phase paths impairment which causes both in-band and out-of-band distortions, a 960-MHz delay tuner is designed for precise amplitude and phase alignment. Furthermore, two digital pre-distortion algorithms for digital power amplifier (DPA) are implemented and compared. Importantly, an on-chip dc–dc converter is included for direct battery connection and output power control. Boosted cascode gate bias improves PA efficiency at low power region. The proposed design is fabricated using a 55-nm RF CMOS technology. This DPA including digital amplitude modulation (AM) filtering achieves peak power of +21.9 dBm with 41% drain efficiency in continuous-wave measurements. It achieves EVM of 2.9% with 20-MHz IEEE 802.11ac compliance of 256-QAM OFDM signal, and also achieves EVM of 4.5% (CC0)/4.8% (CC1) with 40-MHz LTE-A carrier aggregation compliance of 64-QAM OFDM signal.

Wideband Digital Power Amplifiers With Efficiency Improvement Using 40-nm LP CMOS Technology

In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm $^2$ and 0.24 mm $^2$ , respectively.

A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA

This paper presents a single-chip digital-intensive polar transmitter for WCDMA and WLAN integrating a low-phase-noise all-digital phase-locked loop (ADPLL), a digitally-controlled wideband phase/amplitude modulator, and a calibration-free high-linearity power amplifier. From the ADPLL, the 1.7–2.5 GHz LO signal is generated together with a ${\div} $ 1.5 frequency divider to eliminate DCO pulling. The phase noise of the ADPLL is optimized by using a linearized stochastic TDC with 3 ps resolution and a Class-C quadrature DCO (QDCO) with embedded quadrature phase shifter and quantization-noise filter. A 2-segment $\Sigma \Delta$ switching phase modulator enhances the PM bandwidth up to 200 MHz, and a digital polar amplifier employs AM-replica linearization to eliminate AM pre-distortion. The TX achieves a ${-}$ 1 dB output compression point of 22.8 dBm with an overall system efficiency of 27.6% and measures EVM of 4% for a 20 MHz 64-QAM signal at an output power of 13.8 dBm.

Performance Limits, Design and Implementation of mm-Wave SiGe HBT Class-E and Stacked Class-E Power Amplifiers

<?Pub Dtl=""?> Design equations and performance limits of Class-E power amplifiers at mm-waves, including the limitations imposed by active and passive devices in a given technology, are presented in this paper. A beyond nominal breakdown voltage Class-E design methodology for SiGe HBT power amplifiers is proposed to generate high output power while maintaining high Class-E efficiency. A mm-wave SiGe stacked Class-E architecture is also introduced to increase the overall voltage swing, with each series stacked device operating in the beyond nominal breakdown mode. The mm-wave beyond <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$BV_{\rm CEO}$</tex></formula> operation of SiGe HBTs has been demonstrated experimentally in an integrated 45 GHz Class-E power amplifier fabricated in a 0.13 µm SiGe BiCMOS process with 20 dBm measured output power at 31.5% peak power-added efficiency (PAE). The series stacking of mm-wave Class-E power amplifier concept is also verified by fabricating double-stacked and triple-stacked SiGe HBT power amplifiers in 0.13 µm SiGe BiCMOS process which demonstrate a measured output power of 23.4 dBm at 41 GHz with peak PAE of 34.9%. High power, highly efficient, switching power amplifier unit cells presented in this paper can facilitate realization of efficient Watt-level mm-wave digital polar transmitters.

A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization

This paper presents a 65 nm CMOS digital polar transmitter with on-chip power amplifier (PA) for WCDMA and WLAN application. The proposed architecture is composed of a digital interpolation filter for up-sampling of the input amplitude-control word (ACW), a 9-bit switched-capacitor array for the digital polar modulation (DPM), and a 6-bit PA array to achieve the output power range for the target applications. A linearization technique is implemented by adaptively changing the PA bias voltage according to the RF envelope. To generate this bias voltage, the RF envelope of the PA input is extracted by a digital-to-analog converter (DAC) with the ACW signals as its input. A scaled replica of the PA, which only needs to operate at the Amplitude Modulation (AM) frequency, is employed to sense the RF envelope and to regulate the PA bias voltage with an analog feedback loop to minimize the distortion in the AM path. Even without amplitude pre-distortion, the transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN 54-Mb/s 64-QAM OFDM respectively while providing a peak output power of 20.4 dBm with PAE 32.3%.

0.7–1.8 GHz multiband digital polar transmitter using watt-class current-mode class-D CMOS power amplifier and digital envelope modulation technique for reduced spurious emissions

A polar transmitter driven by digital input signals for envelope and phase is demonstrated, using a band-switching output resonator to achieve multiband operation. A new digital pulse width modulation algorithm is also shown to partially suppress spurious signals associated with the digital input envelope signal. The transmitter consists of a current-mode class-D (CMCD) CMOS power amplifier (PA), together with a buck converter with a dead-time generator for improved efficiency. The CMCD PA is tuned by band-switching capacitors that can handle up to 9 V, and is measured to have approximately 30 dBm output power with 31–35% drain efficiency under single-tone testing. The proposed spurious signal reduction technique works to partially suppress quantization noise without increasing power consumption. Overall efficiencies of 27.1/25.6% are obtained at 30.2/28.9 dBm continuous wave (CW) output powers and 0.85/1.75 GHz carrier frequencies, respectively. Spur suppression of 9–10 dB peak is achieved when the proposed algorithm is applied with wideband code division multiple access (WCDMA) modulation.

A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters

In this work, we have demonstrated a fully-integrated, high-efficiency CMOS inverse Class-D PA. Such efficient switching amplifiers can form the core of mixed-signal polar transmitters. A comprehensive analytical framework has been developed to determine optimum component values to maximize efficiency. Operating from a 1-V supply, the PA achieves a peak efficiency of 44% without any RF process options. This is comparable to that of state-of-the-art CMOS switching PAs despite using a much simpler output matching network.

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter

A new linearization scheme is proposed, which compensates for nonlinear distortions experienced in the amplitude-modulation path of a digital polar EDGE transmitter integrated in a 65-nm CMOS transceiver system-on-chip (SoC) based on the Digital RF Processor (DRP) technology. The measured amplitude and phase distortions are stored in lookup tables and used for predistortion without requiring inversion computations, thus achieving significant complexity reduction. Adaptive linear interpolation along with adaptive resolution enhancement provides the desired performance across power levels. With the presented scheme, the transmitter's measured performance significantly exceeds the EDGE specifications with an error vector magnitude (EVM) of typically 3% and a close-in modulated spectrum of -64 dB at a 400-kHz offset from the carrier frequency.

Digital polar transmitter for ultra-wideband system using OFDM modulation

A behavioural model for a digital polar transmitter, consisting of a combined array of parallel amplifiers, is presented. Gain mismatch is modelled for each amplifier. The effects of the resolution and the mismatch on the error vector magnitude for ultra-wideband are studied.