Digital PLLs Research Articles

Digital PLLs for phase noise channels: a concept based on the Tikhonov distribution

Digital PLLs for phase noise channels: a concept based on the Tikhonov distribution

Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise

Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise

IEEE SSCS Utah Chapter Update [Chapters

The IEEE Solid-State Circuits Society (SSCS) Utah Chapter hosted two seminars to close out 2022. The first seminar was held as a hybrid event on 15 September, with a virtual presentation by Distinguished Lecturer Dr. Mike Shuo-Wei Chen. Local participants were able to meet in person at the College of Engineering, Brigham Young University. Dr. Chen, University of Southern California, shared two presentations. The first presentation, “Trend in Digital PLL Design and New Opportunities in Spur Cancellation,” introduced methods for adaptively cancelling spurs in digital PLLs and discussed dither-based spur cancellation techniques. In the second presentation, “High-Performance Digital-to-Analog Converter Design: A Path Toward Digital Transmitter,” Dr. Chen introduced a dual-rate hybrid DAC architecture for accurate high-speed outputs. He also shared PA architectures with subharmonic switching to improve transmission efficiencies. Dr. Chen’s presentation was very well received by attending students and SSCS members.

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent gain. The theoretical predictions differ by less than 1% from the simulation results obtained using a behavioral model, in all typical cases: dominant reference noise, dominant DCO noise, and comparable contributions. An accurate discrete-time model that takes into account the time-variant effect arising from the multirate nature of a digital phase-locked loop (DPLL) is used, along with the provided estimation of the jitter, to predict the output and input-referred phase noise spectra. An excellent match with the simulated spectra is achieved for all the different operating conditions.

Jitter Minimization in Digital PLLs with Mid-Rise TDCs

This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limit-cycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise characteristic, and the optimal TDC resolution is determined. The analysis, which account for TDC mismatches, shows that, compared to the 1-bit one, the 2-bit time-to-digital converter can substantially reduce the quantization noise in the case of dominant random-walk noise at the TDC input. Moving to the $N_{b}$ -bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of $N_{b}=2$ seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paper.

Fractional‐ N PLL with multi‐element fractional divider for noise reduction

A novel technique to suppress quantisation noise in a ΔΣ fractional- N phase-locked loop (PLL) using a fine-resolution multi-element fractional divider is presented. The proposed technique suppresses noise uniformly over the entire frequency range. It is mostly digital and is applicable for both analogue and digital PLLs. The proposed technique with an eight-element fractional divider can suppress the quantisation noise by 18 dB compared with a conventional fractional- N PLL.

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

This paper presents the first published fully-integrated digital fractional- N PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL's quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL (ΔΣ-PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLL's loop filter to the point where it is not a dominant contributor to the PLL's output phase noise. However, in contrast to a ΔΣ-PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a ΔΣ-PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLL's digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is -123, -135, and -150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLL's power consumption is lower than previously published digital PLLs with comparable phase noise performance.

DL Michael H. Perrott Speaks on System-Level Simulation of Time-Based Circuits and Digital PLLs at SSCS Lehigh Valley [Chapters

DL Michael H. Perrott Speaks on System-Level Simulation of Time-Based Circuits and Digital PLLs at SSCS Lehigh Valley [Chapters

Towards SET Mitigation in RF Digital PLLs: From Error Characterization to Radiation Hardening Considerations

In this work, the characteristics of single-event transient (SET) generation and propagation are analyzed in a digital phase-locked loop (DPLL) circuit, designed to achieve speeds applicable to mixed-signal RF operations. The analysis shows that the sensitivity of a DPLL system is strongly dependent on which of its modules is subjected to ionizing radiation. Computer simulations of single-event transients on the phase-frequency detector module and the voltage-controlled oscillator module indicate that their radiation responses have a negligible impact on the DPLL normal operations. More importantly, our findings identify the sensitivity of the charge pump module as the dominant contributor to the radiation vulnerability of the DPLL system. The charge pump incorporates a design element that is favorable to achieving high-speed operations, but simultaneously introduces a circuit configuration that can be easily perturbed by the impact of a heavy-ion. Hardening by design techniques that could be used to mitigate this issue are also discussed

Delay and jitter property of mutually synchronized networks using complete digital plls

AbstractThis paper discusses the effect of delay propagation in the mutually synchronized network using completely digital PLL. A difference equation is derived with the risetime differences among nodes as the variables. The dynamical properties of the mutually synchronized network including the propagation delay, the steady‐state and the jitter characteristic are derived. As a result, the following properties are demonstrated. When the delay is less than half of the steady‐state period, the dynamical property and the jitter of the network are the same as those of the network, without delay. However, when it is larger than the half‐period, the dynamical property and the jitter of the network are affected by the delay. It is also shown that the jitter suppression of the N‐node mutually synchronized network is approximately proportional to the number of nodes N.

All digital phase‐locked loop with nonlinear multilevel quantized phase comparator

AbstractThe PLL has assumed an important role and is widely employed in communication systems. In recent years efforts have been directed toward implementation of PLLs by means of digital circuitry and a large number of digital PLLs (DPLLs) have been reported. the binary quantized DPLL has received particular attention. However, in a first‐order PLL, pull‐in performance and operation in the lock mode have conflicting requirements and, in addition, a steadyphase difference is produced when the input signal has a frequency offset, resulting in unfavorable effects on the communication system. In the past, these problems have been resolved by employing a second‐order loop but, due to the resultant complexity of the loop, this causes several problems, including poor transient response and integrator drift. In this paper we present a new DPLL incorporating a nonlinear multilevel quantized phase comparator (with characteristic τ sgn ψ ‐ ψ). By means of its phase comparator characteristic this loop improves the steady‐state phase error and also affords more rapid transient response as well as other features including excellent jitter suppression within the pull‐in range. Performance characteristics of the proposed loop are determined theoretically and are verified by experiment.

Analysis of a binary quantized dpll by equivalent analog model

AbstractA binary quantized digital phase‐locked loop (DPLL) is a class of digital PLLs having advantage of its simplicity and high reliability. This class of DPLL has been analyzed by applying Markov theory. However, this method has a limited range of applications and the numerical solutions of the performances have not been obtained without using a computer. In this paper, a binary quantized DPLL is analyzed by replacing the DPLL with the equivalent linear and nonlinear analog PLL. This equivalent method of analysis can be applied to more general cases. The numerical results agree with those of experiments.