Digital Phase-sensitive Demodulation Research Articles

Survey of signal clamping for digital phase sensitive detector.

Electrical capacitance tomography (ECT) is a multiphase flow detection technology, which has the advantages of nonradioactive, noninvasive, and on-line visualization measurements. In ECT measurements, the digital phase sensitive demodulation (PSD) plays an important role in guaranteeing the accuracy of small capacitance measurements. Generally, the clamping circuit is implemented to protect the A/D converter. In the measuring circuit, a programmable gain amplifier is usually employed to expand the dynamic range of PSD. However, the measured signal may exceed the measurement range from time to time, which induces the signal clamping effect. In this case, the digital PSD will present large errors in the capacitance measurements. In consideration of the frequency spectrum characteristic of the clamped signal, two digital PSD methods have been proposed. The proposed methods have been implemented in a field programmable gate array based measurement system. The experimental results show that the proposed multisine PSD method could expand the dynamic range by a factor of 5, at a relatively low error, i.e., ≤2%.

New capacitively coupled electrical resistance tomography (CCERT) system

This work focuses on the hardware improvement of a CCERT system. An inductor module is developed by the simulated inductor technique. With the inductive reactance of the developed inductor module, the capacitive reactance of the coupling capacitances is eliminated by the impedance elimination principle and the unfavorable influences of the coupling capacitances are overcome. The digital phase-sensitive demodulation technique is introduced to obtain the total impedance of gas–liquid two-phase flow, including the real part, the imaginary part and the amplitude. Finally, a new CCERT system prototype is developed. Impedance measurement experiments and practical image reconstruction experiments are conducted. The research results show that the design of the new CCERT system is successful. The unfavorable influences of the coupling capacitances are effectively overcome and the signal-to-noise ratio of the new system is improved. Compared with the previous CCERT system, the accuracy of the impedance measurement and the quality of image reconstruction of the new system are improved. Meanwhile, the new CCERT system can also obtain the total impedance of gas–liquid two-phase flow.

Online measurement of conductivity/permittivity of fluid by a new contactless impedance sensor.

By expanding the contactless conductivity detection (CCD) technique to contactless impedance detection technique, a new contactless impedance sensor is designed to implement the online measurement for both the conductivity of a conductive fluid and the permittivity of a non-conductive fluid. In the new contactless impedance sensor, a new simulated inductor is developed to overcome the unfavorable influences of the coupling capacitances by impedance elimination principle, and the digital phase-sensitive demodulation (DPSD) technique is adopted to realize the impedance measurement. To verify the effectiveness of the new contactless impedance sensor, simulation experiments (using different resistors, capacitors, and their combinations) and practical fluid experiments (using KCl solutions with different concentrations, eight organic solvents, and pure water) are carried out. The experimental results show that the development of the new contactless impedance sensor is successful and the conductivity/permittivity measurement performance of the new sensor is satisfactory. The maximum relative error of conductivity measurement is 3.1% and the maximum relative error of permittivity measurement is 5.5%. Compared with the conventional conductivity/permittivity sensors, the new sensor can implement the contactless online measurement of both the two electrical parameters of fluid. Meanwhile, the new contactless impedance sensor is suitable for industrial applications and has the advantages of simple construction and low cost.

A New Dual-Modality ECT/ERT Technique Based on C4D Principle

Based on the measurement principle of capacitively coupled contactless conductivity detection, a new dual-modality electrical capacitance tomography (ECT)/electrical resistance tomography (ERT) technique is proposed, and hence, a new integrated dual-modality ECT/ERT system is developed. First, with the digital phase-sensitive demodulation technique, the capacitance and resistance measurements of the fluid are obtained simultaneously. Then, a modality recognition method, which is on the basis of the $k$ -nearest neighbor algorithm, is proposed to automatically implement the modality switching between two different modalities (ECT modality and ERT modality). Finally, with the modality recognition result, ECT or ERT modality is selected to reconstruct the cross-sectional image of the permittivity or the conductivity distribution of the fluid. Static experiments and dynamic experiments were carried out. Experimental results demonstrate the feasibility of the proposed dual-modality ECT/ERT technique and the effectiveness of the developed dual-modality ECT/ERT system. The research results also indicate that the proposed modality recognition method is effective and can determine the correct modality. The qualities of the reconstructed images in ECT modality or ERT modality are satisfactory.

Impulsive noise reduction in digital phase-sensitive demodulation by nonlinear filtering

Phase-sensitive demodulation is widely used in many systems, e.g. impedance measurement, communication, sonar and radar. In most cases, white noise is assumed in system design and analysis. However, impulsive noise is often encountered in many applications, which imposes challenges for a phase-sensitive demodulator (PSD). This paper presents a nonlinear filter for removing impulsive noise prior to the PSD. Unlike its linear counterparts, it is analysed in the time domain rather than in the frequency domain, making it easier to implement. The performance of the proposed method is compared to a standard PSD with a low-pass filter to suppress the impulsive noise and the theoretical limits of the signal-to-noise ratio (SNR) is analysed. The theoretical prediction has been validated by numerical simulation and experiment. Experimental results show that the proposed method can achieve SNR improvement of 10.8 dB or greater when impulse rate α = 0.01. Statistical analysis shows that 97.2% of the impulses can be rejected by the median filter of length 3 when impulse rate is less than or equal to 0.1.

Design of Embedded Bio-Impedance Analyzer Based on Digital Auto Balancing Bridge Method

This paper presented the design of a novel embedded bio-impedance analyzer based on digital auto-balancing bridge method. The hardware architecture of the system mainly consists of FPGA, ADC, DACs, USB controller and so on. Many DSP algorithms such as direct digital synthesis, digital phase sensitive demodulation, digital modulation and digital filter were implemented in FPGA to realize the auto balancing function of the bridge circuit. Simulation results show that the system has good performance from low frequency up to 10 MHz. For the advantages of cost-efficient and high stability, it is suitable for BIA application.

Biomaterial Impedance Analyzer Based on Digital Auto Balancing Bridge

This paper presents the design method of a novel biomaterial impedance analyzer based on digital auto balancing bridge method. The system hardware mainly consists of FPGA, ADC, DACs and operational amplifiers. Many DSP algorithms such as direct digital frequency synthesis (DDS), digital phase sensitive demodulation (DPSD), digital modulation and digital filter are implemented in FPGA to realize the auto balancing function of the bridge circuit. Simulation results show that the system has good performance from low frequency to 10MHz. It is suitable for EIS application in biomaterial analysis.

A high-performance digital system for electrical capacitance tomography

This paper describes a recently developed digital-based data acquisition system for electrical capacitance tomography (ECT). The system consists of high-capacity field-programmable gate arrays (FPGA) and fast data conversion circuits together with a specific signal processing method. In this system, digital phase-sensitive demodulation is implemented. A specific data acquisition scheme is employed to deal with residual charges in each measurement, resulting in a high signal-to-noise ratio (SNR) at high excitation frequency. A high-speed USB interface is employed between the FPGA and a host PC. Software in Visual C++ has been developed to accomplish operational functions. Various tests were performed to evaluate the system, e.g. frame rate, SNR, noise level, linearity, and static and dynamic imaging. The SNR is 60.3 dB at 1542 frames s−1 for a 12-electrode sensor. The mean absolute error between the measured capacitance and the linear fit value is 1.6 fF. The standard deviation of the measurements is in the order of 0.1 fF. The dynamic imaging test demonstrates the advantages of high temporal resolution of the system. The experimental results indicate that the digital signal processing devices can be used to construct a high-performance ECT system.

Design and implementation of a DSP-based digital phase sensitive demodulation for an EIT system

Electrical Impedance Tomography (EIT) is a non-invasive imaging method that can generate image of impedance distribution inside an object. In this imaging method, measured voltages are complex quantities that contain real and imaginary parts. To increase the accuracy of image reconstruction in EIT systems, it is necessary to utilize both real and imaginary parts of measured voltages. Phase sensitive demodulator can accurately specify the two parts of measured voltages. In this paper, a digital phase sensitive demodulator (DPSD) has been designed and implemented using a DSP board. Floating point 32-bit arithmetic with high speed of 225 MHz of the DSP core allows this digital demodulator to accurately measure real and imaginary parts of measured voltages with a desired SNR in an EIT system. This paper describes the theory and implementation of DPSD on a TMS320C6713 DSP board. Next, simulation data generated by the Code Composer Studio software and the data of an EIT phantom are applied to the DPSD. The simulation data results show a 0.12 degree phase error and a 0.37 % amplitude error with high SNR of 130.6 dB. The EIT phantom results present the 0.76 degree phase error and the 0.91 % amplitude error.

Performance evaluation of KHU Mark2 parallel multi-frequency EIT system

We describe a new parallel multi-frequency EIT system, KHU Mark2. It is based on the impedance measurement module (IMM), which comprises a single-ended constant current source and a voltmeter. Each IMM has an FPGA for its independent operations including current injection at multiple frequencies, voltage amplification, ADC, digital phase-sensitive demodulation and intra-networking with a main controller of the system. The main controller is based on a DSP and an isolated USB for its connection to a PC. There is an FPGA-based intranet controller, which arbitrates data exchanges between the DSP and multiple IMMs. Unlike its precursor, KHU Mark1, it is a true parallel system with no switching for both current injection and voltage sensing. The small size of the IMM results in a much reduced dimension of a multi-channel system. The KHU Mark2 can be assembled in any channels between 1 and 64. Depending on a chosen application, we custom design an analog backplane that interfaces multiple IMMs with electrodes. Special care was given to the system calibration to maximize its performance in frequency-difference EIT imaging as well as time-difference. Flexibility is the key improvement factor compared with the KHU Mark1. The new system can accommodate any current injection and voltage sensing protocol including the optimal injection current pattern. Reduced size and new internal architecture significantly improved mechanical as well as electrical stability of the system.

Multi-frequency EIT system with radially symmetric architecture: KHU Mark1

We describe the development of a multi-frequency electrical impedance tomography (EIT) system (KHU Mark1) with a single balanced current source and multiple voltmeters. It was primarily designed for imaging brain function with a flexible strategy for addressing electrodes and a frequency range from 10 Hz–500 kHz. The maximal number of voltmeters is 64, and all of them can simultaneously acquire and demodulate voltage signals. Each voltmeter measures a differential voltage between a pair of electrodes. All voltmeters are configured in a radially symmetric architecture in order to optimize the routing of wires and minimize cross-talk. We adopted several techniques from existing EIT systems including digital waveform generation, a Howland current generator with a generalized impedance converter (GIC), digital phase-sensitive demodulation and tri-axial cables. New features of the KHU Mark1 system include multiple GIC circuits to maximize the output impedance of the current source at multiple frequencies. The voltmeter employs contact impedance measurements, data overflow detection, spike noise rejection, automatic gain control and programmable data averaging. The KHU Mark1 system measures both in-phase and quadrature components of trans-impedances. By using a script file describing an operating mode, the system setup can be easily changed. The performance of the developed multi-frequency EIT system was evaluated in terms of a common-mode rejection ratio, signal-to-noise ratio, linearity error and reciprocity error. Time-difference and frequency-difference images of a saline phantom with a banana object are presented showing a frequency-dependent complex conductivity of the banana. Future design of a more innovative system is suggested including miniaturization and wireless techniques.