Digital Phase-locked Loop Architecture Research Articles

A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz.

Analysis and Reduction of Power in all Digital PLL Architecture by using Dynamic PFD with CWSP

Dynamic Phase Frequency Detector with CWSP, Mainly focusing on reducing power consumption, and fast-locking ability and has been used to reduce the delay moments Demonstrated 0.25μm CMOS technology. DTC needed assistance through a phase prediction means substantial energy savings and thus reduces range. A Low power all digital phase Locked Loop (PLL), they have become very attractive because good on a variety of actions, programmability, stability, portability, testability and yield and is better ADPLL Immunogenic noise. The key is to measure the time difference between time-to-digital converter Rising edges of signals. Time-to-digital converter (TDC) ADPLL integrated within. DTC delay Divided reference clock and the feedback clock is like the chain latch design is a comparison between the phase error Low power consumption. The complete ADPLL system improves the performance of the locking ability and the system DTC linearity. The design is implemented using DPFD with CWSP technique was more suitable for high speed phase frequency detector. The proposed system of dynamic phase frequency detector with CWSP has been fabricated and the corresponding power consumed is 75 μW.

A nonuniform DPLL architecture for optimized performance

AbstractThis paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform‐type digital phase‐locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample‐and‐hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal‐to‐noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field‐programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.