Digital Peak Current Mode Control Research Articles

Static Analysis of a Digital Peak Current Mode Control DC–DC Converter Using Current–Frequency Conversion

The purpose of this article is to discuss the design guideline and design chart of the digital peak current mode dc–dc converter using a current–frequency conversion by analyzing its static characteristics. The operation of the proposed method is expressed by equations, and the relationships between controller parameters are derived. This discussion reveals the relationships between the peak current instruction value and the output voltage or peak current, which are necessary for designing the proposed method. Then, the design guideline and design chart are given. The validity of the static characteristic analysis is demonstrated by a prototype, whose design follows the design guideline. An appropriate operation in the steady and static state is also indicated by the experiment. As a result, the validity of the static characteristics and the design guideline of the proposed method can be verified.

Digital peak current mode control of isolated current‐fed push‐pull DC‐DC converter with slope compensation

AbstractThe isolated current‐fed push‐pull dc‐dc converter has some practical advantages such as improved cross regulation characteristics, reduced output noise, and good overall efficiency. Although detailed insight on this converter is available in the literature, the use of digital peak current mode with slope compensation control methodology has not been explicitly presented. This paper discusses digital peak current mode control of a current‐fed push‐pull converter with a novel double digital pulse‐by‐pulse current limiting scheme. Push‐pull topology is implemented on the primary side of an isolation transformer in a dc‐dc bidirectional converter. Achieving this control solution of isolated push‐pull converter is attractive especially in controlling battery power flow in smart micro‐grids. By using a digitally controlled push‐pull converter, the ability to change controller parameters and the use of droop control methods for storage are easier. Furthermore, current mode control provides capability of equal current sharing between parallel converters and eliminates the transformer saturation problem that is common in push‐pull topology. Using continuous time model of the converter, a Type II compensator is designed and implemented in discrete time domain. Digital slope compensation is applied to eliminate the high frequency oscillations caused by current feedback loop. The control method and slope compensation are implemented on STM32F303 mixed‐signal microcontroller. On‐chip analog comparator disabled the PWM output if the sensed current exceeds the reference current until next PWM cycle. The digital controller performance is confirmed by 13 W hardware implementation including fast transient response and stable operation.

Asymmetric slope compensation for digital hybrid current mode control of a three-level flying capacitor buck converter

The three-level flying capacitor (3LFC) buck converter has the potential to provide better efficiency and higher power density as compared to the traditional buck converter. However, due to the flying capacitor?s instability issues, control is challenging. In this paper, the digital hybrid current mode (DHCM) control method, which combines the average and peak current mode control techniques, is modified and implemented to a 3LFC buck converter. For flying capacitor (FC) voltage balancing, a novel asymmetric slope compensation (ASC) technique is presented. The proposed ASC technique achieves FC voltage balancing by adjusting the slope compensation of the two switching pairs asymmetrically, and therefore is applicable to any type of digital peak current mode control (PCM) method. The ASC technique for DHCM control of the 3LFC buck converter is verified in simulations and experimentally with an ARMbased mixed-signal microcontroller on a 250-kHz, 24-V input, and 35-W/4-A output prototype. The overall control method enables the implementation of the 3LFC buck converter for accurate and fast current regulation, and therefore is especially advantageous for LED and laser diode driver applications.

Current Tracking Delay Effect Minimization for Digital Peak Current Mode Control of DC–DC Boost Converter

Digital peak current mode (DPCM) control is widely used for dc–dc converters operating in continuous current mode. However, current tracking delay (CTD) in the system is normally neglected in the modeling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of small signal model. Since CTD degrades the phase margin of the system, equivalent migration of right half plane zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an extended pulsewidth modulation (ExPWM). This optimizes the calculation algorithm and speed, while improving the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments.

A Dual-Mode Driver IC With Monolithic Negative Drive-Voltage Capability and Digital Current-Mode Controller for Depletion-Mode GaN HEMT

This work presents a driver and controller integrated circuit (IC) for depletion-mode gallium nitride (GaN) high-electron-mobility transistors (HEMTs). The dual-mode driver can be configured for cascode-drive (CD) or HEMT-drive (HD) mode. In the CD mode, a cascode low-voltage DMOS is driven to achieve high-speed normally OFF operation. An active clamping circuit is proposed for the DMOS breakdown protection. In the HD mode, an HEMT gate driver with negative drive-voltage capability and programmable slope control is presented. A digital peak current-mode controller is also integrated with the dual-mode driver. The IC was implemented in a 140-nm automotive bipolar-CMOS-DMOS silicon-on-insulator process. The driver/controller IC is copackaged with an optimized 600-V GaN HEMT fabricated in a GaN-on-Si process. The solution was verified to operate at up to 1 MHz in a 35-W boost converter prototype and achieves a programmable switching-node $dv/dt$ of up to 20 V/ns. To the best of the author's knowledge, this is the first monolithic integration of a cascode MOSFET, device driver, and digital current-mode controller that is designed specifically for high-voltage GaN devices.

Power factor corrector with adaptive digital peak current mode control

Цифрові системи керування все частіше застосовуються у силовій електроніці, що обумовлено рядом переваг цифрового керування над аналоговим. У даній статті представлений коректор коефіцієнта потужності з адаптивним цифровим керуванням по піковому струму. Описано принцип керування по піковому струму та вказані переваги і недоліки даного методу. Наведена схема коректора з адаптивним цифровим керуванням. Проведене комп’ютерне моделювання підтвердило працездатність розробленого коректора. Бібл. 14, рис. 6.

High‐performance digital replica of analogue peak current mode control for DC–DC converter

A simple and robust digital peak current mode controller is proposed in this study. The controller replicates an analogue peak current mode control in the discrete domain. The inner current loop has negligible delay, which results in a high controller bandwidth. The controller structure allows the compensation slope to be updated in each switching cycle; therefore, the controller can maintain a high bandwidth over a wide range of operating points. The modelling principles of an analogue peak current mode controller are used to model the proposed controller. For experimental verification, the controller is implemented in a field programmable gate array to control a 100 W buck converter. The measured loop gain of the system correlates very well with the modelling results. The achieved controller crossover frequency is ∼1/10 of the switching frequency which is close to the crossover frequency of analogue peak current mode controllers.

Peak-Valley Current Mode Controlled H-Bridge Inverter with Digital Slope Compensation for Cycle-by-Cycle Current Regulation

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

A Digital Peak Current-Mode Control PFC with Bifurcation Control

A boost power factor correction (PFC) in continuous conduction mode (CCM) by the digital peak current-mode control method with bifurcation control is discussed in this paper. The proposed method is used to prevent the inductor current bifurcation behavior, which is caused by sub-harmonic oscillation when the duty cycle is upon to 50 percent. The bifurcation behavior will increase the inductor current ripple and dissipation, then reduce the Power Factor (PF). Different from the ramp compensation signal performed with analog IC in some papers, a MCU is used to be the controller and also provides the digital compensation function in this paper. With the timer, ADC, PWM, and comparator which are built in the MCU, the necessary parameters will be measured without extra components and additional cost. The proposed method is based on those parameters. In this paper, the MATLAB/Simulink simulation results show the proposed method workable.