Digital Neural Network Research Articles

P pattern recognition based on a probablistic RAM net using n-tuple input mapping

A multilayer digital neural network, based on the probabilistic random access memory (pRAM), is used as a P pattern classifier system. This network presents an elaborate implementation of the n-tuple technique, which has mostly been used for pattern recognition (Bledsoe and Browning, 1959). The network's main properties, discrimination and generalisation, are discussed as a function of the pRAM connectivity. Pyramid networks, based on different pRAM connectivities, are simulated using an enhanced version of global reinforcement learning. n-tuple input mapping based on data analysis is proposed. The results show that combining the permuted data-based input mapping with a pRAM net, using different node connectivities through the pyramid layers, can achieve a good balance of the network's properties, when handling a P pattern classification task. Results are presented for the 10 digit recognition problem, which are motivating and very encouraging.

Hardware-based neural identification: Linear dynamical systems

In this paper, a hardware-based neural identification method is proposed in order to learn the characteristics or structure of a discrete linear dynamical system. Quick or instant identification of unknown dynamical systems is particularly required for practical controls not only in intelligent mechatronics such as, for example, automatic selforganized running of mobile vehicles, but in intelligent self-controlled systems. We developed a new method of hardware-based identification for general dynamical systems using a digital neural network very large scale integration (VLSI) chip, RN-200, where sixteen neurons and a total of 256 synapses are integrated in a 13.73×13.73 mm2 VLSI chip, fabricated using RICOH 0.8 μm complementary metal oxide semiconductor CMOS technology (RICOH, Yokohama, Japan). This paper describes how to implement neural ideitification in both learning and feedfoward processing (recognizing) using a RICOH RN-2000 neurocomputer which consists of seven RN-200 digital neural network VLSI chips.

VLSI compressor design with applications to digital neural networks

A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. In this paper, such a compressor design based on complex complementary pass-transistor logic (C/sup 2/PL) is presented. Some types of 3-2 compressors in C/sup 2/PL are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressors, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct logic (CDL), our simulations show that the C/sup 2/PL compressors have the best performance in power, delay and number of transistors.

A 1.2 GFLOPS neural network chip for high-speed neural network servers

This paper describes a digital neural network chip for high-speed neural network servers. The chip employs single-instruction multiple-data stream (SIMD) architecture consisting of 12 floating-point processing units, a control unit, and a nonlinear function unit. At a 50 MHz clock frequency, the chip achieves a peak speed performance of 1.2 GFLOPS using 24-bit floating-point representation. Two schemes of expanding the network size enable neural tasks requiring over 1 million synapses to be executed. The average speed performances of typical neural network models are also discussed.

Neural network control of robot manipulators

The author describes neural network controllers for robot manipulators in a variety of applications, including position control, force control, parallel-link mechanisms, and digital neural network control. These model-free controllers offer a powerful and robust alternative to adaptive control.

A new architecture for the automatic design of custom digital neural network

This brief presents a novel high-performance architecture for implementation of custom digital feed forward neural networks, without on-line learning capabilities. The proposed methodology covers the entire design flow of a neural application, by addressing the internal neuron's structure, the system level organization of the processing elements, the mapping of the abstract neural topology (obtained through simulation) onto the given digital system and eventually the actual synthesis. Experimental results as well as a brief description of the software environment supporting the proposed methodology are also included.

Generalization in Sigma-Pi Networks

In this paper, we investigate generalization in supervised feedforward Sigma-pi nets with particular reference to means of augmentation of generalization of the network for specific tasks. The work was initiated because logical (digital) neural networks of this type do not function in the same manner as the more normal semi-linear unit, hence the general principle behind Sigma-pi networks generalization required examination, to enable one to put forward means of augmenting their generalization abilities. The paper studies four methods, two of which are novel methodologies for enhancing Sigma-pi networks generalization abilities. The networks are hardware realizable and the Sigma-pi units are logical (digital) nodes that respond to their input patterns in addressable locations, the locations (site-values) then define the probability of the output being a logical ‘1’. In this paper, we evaluate the performance of Sigma-pi nets with perceptual problems (in pattern recognition). This was carried out by compar...

Digital associative memory neural network with optical learning capability

A digital associative memory neural network system with optical learning and recalling capabilities is proposed by using liquid crystal television spatial light modulators and an Optic RAM detector. In spite of the drawback of the limited memory capacity compared with optical analogue associative memory neural network, the proposed optical digital neural network has the advantage of all optical learning and recalling capabilities, thus an all optics network system is easily realized. Some experimental results of the learning and the recalling for character recognitions are presented. This new optical architecture offers compactness of the system and the fast learning and recalling properties. Based on the results, the practical system for the implementation of a faster optical digital associative memory neural network system with ferro-electric liquid crystal SLMs is also proposed.

VLSI Design of Digital Cellular Neural Networks for Image Processing

Biologically inspired analog VLSI systems have attracted more and more studies. For system consistency and for quick application of neural systems, we have established digital models for neuron operations such that the cell operations can be implemented with simple digital adders and multipliers. To provide fast data transfer and minimum reconfiguration for various sizes of networks, the architecture is designed for low hardware complexity and high mask flexibility, and is perfectly suited for VLSI array implementation. The parallel computation model derived here is used to realize parallel array processor architectures for digital neural networks. Some image processing operations have been simulated. The tolerable error rate compared to the analog model and the competent speed performance make this applicable to digital systems and suitable for 2-D signal processing.

Recent VLSI neural networks in Japan

In this article, recent research activities on the development of electronic neural networks in Japan are reviewed. Most of the largest Japanese electronic companies have developed VLSI neural chips using analog, digital or optoelectronic circuits. They have run various neural networks on them. Recently, in Japan, digital approach becomes active. Several fully-digital VLSI chips for on-chip BP learning have been developed, and 2.3 GCUPS (Giga Connection Updates per Second) learning speed has already been attained. Although the numbers of neurons and synapses containable in single digital chips are small, a large neural network can be developed by cascading the chips. By cascading 72 chips, a fully interconnected PDM (Pulse Density Modulating) digital neural network system has been developed. The behavior of the system follows simultaneous nonlinear differential equations and the processing speed amounts to 12 GCPS (Giga Connections per Second). Intensive researches on analog and optoelectronic approaches have also been carried out in Japan. An analog VLSI neural chip attains 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections per Second) processing speed for Boltzmann machine with 1 bit digital output. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.

A neural implementation of complex activation functions for digital VLSI neural networks

A method for implementing a wide range of smooth nonlinear activation functions and their first derivatives in digital neural networks is presented. It uses a simplified neural network which may share most of its components with the native neural network, so that it requires a small amount of additional hardware.

SPIN: THE SEQUENTIAL PIPELINED NEUROEMULATOR

This paper proposes a novel digital neural network architecture referred to as the Sequential PIpelined Neuroemulator or Neurocomputer (SPIN). The SPIN processor emulates neural networks producing high performance with minimum hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. In addition to describing SPIN, performance equations are estimated for the ring systolic, the recurrent systolic array, and the neuromimetic neurocomputer architectures, three previously reported schemes for the emulation of neural networks, and a comparison with the SPIN architecture is reported.

A self-learning digital neural network using wafer-scale LSI

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fuzzy cognitive structure: Foundations, applications and VLSI implementation

Abstract This paper deals with the VLSI implementation of a fuzzy cognitive system. Aspects of fuzzy set theory and neural networks are combined to produce a robust system for expressing uncertainty. A novel architecture for digital neural networks is introduced and analyzed. The system concept is implemented in a three-chin set which incorporates fault tolerance and a cellular automata based built-in self set test. VLSI design trade-offs are explored and details of the implementation are presented.

Digital neural network system based in new concepts on the recall phase dynamics

In this paper we present an electronic system designed to emulate neural networks. Two major restrictions are assumed: discrete synapses (+1,0,−1) and threshold-type neurons. Drawbacks given by restrictions are solved with a more complex learning algorithm that maps real valued configurations for synapses into bipolar ones. The central unit of the system is an ASIC designed in accordance with a new sequential dynamics, which is faster and with better recall characteristics. As a result, the system designed has a fast recall phase and a large number of neurons. A handwritten OCR system is being designed.

A Training Strategy and Functionality Analysis of Digital Multi-Layer Neural Networks

A Training Strategy and Functionality Analysis of Digital Multi-Layer Neural Networks

Digital neural emulators using tree accumulation and communication structures

Three digital artificial neural network processors suitable for the emulation of fully interconnected neural networks are proposed. The processors use N(2) multipliers and an arrangement of tree structures that provide the communication and accumulation function either individually or in a combined manner using communicating adder trees. The performance for the emulation of an N-neuron network for all processors is achieved in 2log(2)N+C time units, where C is a constant equal to the multiplication, neuron activation, and internal fixed delays. The feasibility and characteristics of the proposed configurations to emulate single and/or multiple neural networks simultaneously are discussed, and a comparison with recently proposed neurocomputer architectures is reported.

Classification of crossed immunoelectrophoretic patterns using digital image processing and artificial neural networks.

A method is presented which makes it possible to present crossed immunoelectrophoretic patterns to an artificial neural network. The electrophoretic patterns are presented for the artificial neural network as three-dimensional vectors and it is shown that it is possible with this representation to train the network to learn the patterns and classify them. It was found that the ability to generalize was substantially increased by the addition of noise to the input patterns during training. Furthermore, the addition of noise decreased the number of presentations needed to reach the predetermined error level. The trained neural network was able to classify all distorted patterns correctly within an error range of 1%.

A high-speed digital neural network chip with low-power chain-reaction architecture

A high-speed digital neural network chip adopts a polyhedric discrimination neuron (PDN) model and low-power chain-reaction (LCR) architecture that can reduce the power dissipation to one-fiftieth or less. The chip contains 832 fully implemented digital synapse units that form 13 neurons on a 10.3-mm*14.1-mm die using 0.8- mu m CMOS technology. The synapse weights are updated using an external computer. A computational speed of 8 billion connections per second (GCPS) is achieved with low 54-mW power dissipation. The forward propagation time is 104 ns. These features make it possible to implement large-scale neural network chips and systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Self-Organising Strategy for Digital Neural Networks

A Self-Organising Strategy for Digital Neural Networks