Digital Microprocessor Research Articles

Design of 32 bit Parallel Prefix Adders

In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values. Keywords− prefix adder, carry operator, Kogge-Stone, Brent-Kung, Ladner-Fischer. I. Introduction Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders. In electronics, an adder or summer is a digital circuits(7) that performs addition of numbers. In many computers and other kind of processors, adders are other parts of the processor, many computers and other kinds of processors, where they are used to calculate addresses, table and similar. The binary adder(7,10) is the one type of element in most digital circuit designs including digital signal processors(DSP) and microprocessor data path units. Therefore fast and accurate operation of digital system depends on the performance of adders (6). Hence improving the performance of adder is the main area of research in VLSI(10) system design. The Conventional adders discussed in section II. The details of R Kogge- Stone adder, Brent-Kung adder and Ladner- Fischer adders are discussed, and the implementation of proposed system is described in section III. The performance and simulation results were presented and discussed in section IV.

Multi-axis motion controller for robotic applications implemented on an FPGA

This paper presents the design of a field-programmable gate array (FPGA)-based motion controller for robotic applications. In contrast to digital signal processor and microprocessor implementations, the control period of this system is fixed. Foregoing implementations on FPGA require microprocessor-based platforms for data interchange tasks consuming a large amount of resources; consequently, they could not be implemented on low logic density devices, or they use IP cores which limits the implementation of the system to only certain device families. This new motion controller architecture integrates control and communication modules in a single chip which permits an increase to the number of axis according to the system requirements. The proposed design presents a low consumption of logic resources; therefore, a considerable cost saving per axis is achieved. The system test has been carried out with a three-degree of freedom selective compliant assembly robot arm robot and a standard PC as master device. The digital filter parameters have been tuned by using a crossover frequency method. Step and profiled motion responses obtained show very good performance.

VLSI Implementation of Heterogeneous Adder for Performance Optimization

An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always in larger area occupied by circuit on chip and vice-versa. In order to design an optimized adder circuit which provides area/delay tradeoffs, we studied different available parallel, synchronous adders and proposed a new adder based on combination of them. In this paper, we proposed a new type of adder architecture known as heterogeneous adder that consists of concatenation of sub-adder (homogeneous adder) of different types. The heterogeneous adder architecture provides better design tradeoffs in terms of area and delay characteristics.

Performance Evaluation of Multi-Axis CNC Machine Tools by Interferometry Principle using Laser Calibration System

Advancement in digital electronics and microprocessors has made the manufacturing sector capable to generate complex components within small tolerance zone in nanometre range at one machining center. All motion control systems have some form of position feed back system fitted with the machine. But the systems are not perfectly accurate due to the errors in the positioning performance of the machine tools which will change over time to time due to wear, damage and environmental effect. The complex structure of multi-axis CNC machine tools produces an inaccuracy at the tool tip caused by kinematic parameter deviations resulting in manufacturing errors, assembly error and quasi-static errors. Analysis of these errors using a laser measurement system provides the user with a way to achieve better accuracy, and hence higher quality output from these processes. In this paper, characteristic of the positioning errors of the axes of multi-axis CNC machine tools and the technique to measure the errors by a laser interferometer calibration system have been discussed and the positioning accuracy of the machine each axis has been verified.

Comparison of Analog and Digital Self-Powered Systems in Multimodal Vibration Suppression

This paper compares our analog and digital self-powered systems for vibration suppression, and shows experimental results of multimodal vibration suppression for both self-powered systems. The experimental results are evaluated in light of the damping performance and adaptability under various vibrational conditions. We demonstrate various examples of our innovative vibration suppression method, called “digital self-powered.” Proper status switching of an electric circuit made up of an inductor and a selective switch connected to a piezoelectric transducer attenuates the vibrations. The control logic calculation and the switching events are performed with a digital microprocessor that is driven by the electrical energy converted from the mechanical vibration energy. Therefore, this vibration suppression system runs without any external power supply. The self-powering feature makes this suppression method useful in various applications. To realize an ideal vibration suppression system that is both self-powered and effective in suppressing multimode vibration, sophisticated control logic is implemented in the digital microprocessor. We demonstrate that our digital self-powered system can reduce the vibrational displacements of a randomly excited multimodal structure, by as much as 35.5%.

A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits

A Wallace tree multiplier using modified booth algorithm is proposed in this paper. It is an improved version of tree based Wallace tree multiplier (1) architecture. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of booth algorithm, 5:2, 4:2, and 3:2 compressor adders. An efficient VerilogHDL code has been written, successfully simulated and synthesized for Xilinx FPGA vertex-6 low power (Xc6vlx75tl-1Lff484) device, using Xilinx 12.2 ISE and XST. The result shows that the proposed architecture is around 67% faster than the existing Wallace-tree multiplier. I. INTRODUCTION A multitude of various multiplier architectures have been published in the literature, during the past few decades. The multiplier is one of the key hardware blocks in most of the digital and high performance systems such as digital signal processors and microprocessors. With the recent advances in technology, many researchers have worked on the design of increasingly more efficient multipliers. They aim at offering higher speed and lower power consumption even while occupying reduced silicon area. This makes them compatible for various complex and portable VLSI circuit implementations. However, the fact remains that the area and speed are two conflicting performance constraints. Hence, innovating increased speed always results in larger area. In this paper, we arrive at a better trade-off between the two, by realizing a marginally increased speed performance through a small rise in the number of transistors. The new architecture enhances the speed performance of the widely acknowledged Wallace tree multiplier. The structural optimization is performed on the conventional Wallace multiplier, in such a way that the latency of the total circuit reduces considerably. The Wallace tree basically multiplies two unsigned integers. The conventional Wallace tree multiplier architecture comprises of an AND array for computing the partial products, a carry save adder for adding the partial products so obtained and a carry propagate adder in the final stage of addition. In the proposed architecture, partial product generation and reduction is accomplished by the use of booth algorithm, 3:2, and 4:2, 5:2 compressor structures.

Implementation and Performance Evaluation of Prefix Adders uing FPGAs

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs including digital signal processors and microprocessor data path units. The final carry is generated ahead to the generation of the sum which leads extensive research focused on reduction in circuit complexity and power consumption of the adder. In VLSI implementation, parallel-prefix adders are known to have the best performance. This paper investigates four types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, spanning tree, Brent kung Adder) and compare them to the simple Ripple Carry Adder and Carry Skip Adder. These designs of varied bit-widths are simulated using model-sim simulator of 6.4 version and implemented on a Xilinx 10.1 version Spartan 3E FPGA. These fast carry-chain carry-tree adders support the bit width up to 256. We report on the area requirements and reduction in circuit complexity for a variety of classical parallel prefix adder structures. Keywords-FPGA, Prefix Adder, ALU, Xilinx, VLSI, CLA, Simulation, Synthesis

Power Comparison of CMOS and Adiabatic Full Adder Circuits

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

Design of a novel low power 8-transistor 1-bit full adder cell

An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

A Comparative Evaluation of Temperature Changes in the Pulpal Chamber during Direct Fabrication of Provisional Restorations: An In Vitro Study

To compare the temperature changes in the pulpal chamber during fabrication of provisional restorations by direct method. A total of 108 three-unit FPD provisional restorations were fabricated on a study model and divided into three main groups according to the material used for the fabrication of matrix. Group A-Alginate impression index group, Group B-Polyvinylsiloxane putty impression index group, Group C-Vacuum formed template group. Each group comprising of 36 specimens, was subdivided into three subgroups based on the provisional restorative material used: polymethylmethacrylate (subgroup 1), polyethylmethacrylate (subgroup 2), bis-acryl composite resin (subgroup 3). Intrapulpal temperature changes were observed with the help of a thermocouple probe (connected to a digital microprocessor thermometer) inserted into the pulp chamber of an extracted mandibular second molar mounted on a study model, during the fabrication of provisional restorations by direct method. The subgroups mean temperature rise observed in Group A-A1, A2, A3 was 2.6250±0.2491, 1.0500±0.1382, 0.4083±0.1165, respectively. The subgroups mean temperature rise observed in Group B-B1, B2, B3 was 4.6250±0.2454, 3.3750±0.3415, 2.5917±0.2678, respectively. The subgroups mean temperature rise observed in Group C-C1, C2, C3 was 4.7694±1.8361, 3.0611±1.5767, 2.3806±1.5713, respectively. The observations were statistically significant. The intrapulpal temperature rise during fabrication of a provisional restoration depended both on the type of provisional restorative material and the type of matrix used. The clinician should choose carefully the resin and the matrix material while fabricating provisional restorations with direct method.

An Embedded- Technology-Based Web Server Design of Digital Home

The development of information technology sped up the pace of the reform in modern family life. People have a higher demand for safety, comfort and efficiency of home environment. The conception about ”Smart Home”, “Digital Earth”, “Digital Comfortable Community”, “Wisdom Earth” are being put forward with the rapid development of the property of digital home microprocessor. The technology of digital home embedded web server will become the bottleneck in the development of the digital home. Therefore, this paper used the ARM9EJ-S processor and Linux operation system, combined with the mature technique of Java and MVC (Model View Controller) and designed a kind of digital home embedded web server. The validity and efficiency of the system was validated via test-experiment. The results show that this system has many advantages, such as small volume, lower power consumption, lower cost, safety and reliability, easy to install and to maintain, good practicality and so on. People can control everything in the home whenever and wherever they are through the Internet.

PH-changes during Intracoronal Bleaching: An in vivo Study

This study aimed to measure pH changes during 14 days intracoronal bleaching with hydrogen peroxide/sodium perborate and carbamide peroxide/sodium perborate. Twenty patients presenting endodontically treated central maxillary incisors with color alterations were divided in two groups (n = 10): Group CP + SP: 37% carbamide peroxide + sodium perborate paste; Group HP + SP: 30% hydrogen peroxide + sodium perborate paste. The pH values were measured using a digital microprocessor at different times: Baseline, 2, 7 and 14 days. Data were analyzed with two-way ANOVA followed by Tukey's test (α = 0.05). ANOVA showed p < 0.00 which indicated significant difference between the groups. The mean values (± sd) and the results of the Tukey´s test were: HP + SP/14 days-7.98 (±0.58)a; HP + SP/7 days-8.59 (±0.18)b; HP + SP/2 days- 8.83 (±0.32)bc; HP + SP/Baseline-8.83 (±0.01)bc; CP + SP/ Baseline-8.89 (±0.01)bc; CP + SP/14 days-9.11 (±0.58)cd; CP + SP/7 days-9.54 (±0.16)de; CP + SP/2 days-9.66 (±0.08) de. The group HP + SP resulted in significantly lower pH values compared with group CP + SP. It can be concluded that both associations showed alkaline pH values; however, there was significant reduction in the pH values of the 30% hydrogen peroxide associated with sodium perborate after 14 days. The association of hydrogen peroxide and carbamide peroxide with sodium perborate paste presented alkaline characteristics during the 14-day evaluated period. Thus, regarding pH changes, both associations can be considered safe as intracoronal bleaching agents.

TRACTOR ENGINE LOAD AND FUEL CONSUMPTION IN ROAD CONSTRUCTION WORKS

Tractor load influences engine work parameters having an influence on the working economy and productivity of the complete tractor aggregate. The operational economy and productivity of the tractor is mostly evident when its engine power is utilized at least at 80% and engine speed is as low as possible. The paper analyses the engine parameters of tractor Massey Ferguson MF 8480 during the operational period of road construction works. Control tests on the parameters of the engine load of the tractor engine in combination with the employed milling equipment WS 2500 produced by the company ‘Wirtgen’ were performed. The study was carried out using engine load tables and graphs collected and stored in the so called ECU Load Profileintegrated in Electronic Engine Control Units. Theoretical analysis was made and an equation presented to establish the relation between engine power, engine speed and the quantities of cyclic fuel consumption. The study results present the distribution graphs of work time and fuel consumption at different engine speed during the operational period. The paper also indicates engine load and fuel consumption graphs of the tractor in combination with milling equipment. The article has also disclosed that the analysis of engine speed and load modes using information obtained from tractor‐integrated digital microprocessors reveals the operation quality of the tractor.

스텝응답을 이용한 3매개변수 모델의 식별

This paper provides an identification method for three-parameter models i.e. first order with dead time models and second order with dead time models. The proposed identification method is based on step response and can be easily implemented using digital microprocessors. The proposed method first identifies the order of the plant i.e. first order or second order from the behavior of the plant with constant input. After the order of the plant is determined, a test step input is applied to the system and the three parameters of the plant are obtained from the corresponding response of the plant. The output of the plant need not to be zero when the test signal is applied. The efficacy of proposed algorithms is verified through simulation and experiment.

Enhancement of accuracy of multi-axis machine tools through error measurement and compensation of errors using laser interferometry technique

The present era is witnessing advancement in digital electronics and microprocessor which enables manufacturing sector capable to produce complex components within small tolerance zone in the tune of nanometre and at one machining center. All motion control systems have some form of position feed back system fitted with the machine. Such systems are not generally accurate due to the errors in the positioning performance of the machine tool which will change over time to time due to wear, damage and environmental effects. The complex structure of multi-axis CNC machine tools produce an inaccuracy at the tool tip caused by kinematic parameter deviations resulting in manufacturing errors, assembly errors or quasi-static errors. Analysis of these errors using a laser measurement system provides the manufacturers a way to achieve better accuracy and hence higher quality output from these processes. In this communication, techniques to measure the linear positional errors of axes of CNC machine tools by a laser interferometer calibration system and accuracy enhancement using the data obtained from the calibration cycle by feeding into the machine’s controller with the help of linear error compensation package are discussed.

Silicon Is About to Change the World - Again [Point of View

This paper describes several examples of benefits derived from replacing mechanics with power electronics, including SkyTran-a silicon-based transportation system. However, the new power electronics has much wider application than SkyTran alone. Mating diverse distributed power sources to the electric grid is challenging, but SkyTran's power electronics partner, One-Cycle Control, Inc., a spinoff of California Institute of Technology (Caltech) and the University of California, Irvine, has shown how agile power control can help. Interestingly, One-Cycle Control accomplishes this with no digital signal processing or microprocessor software.

Single front-end SOC for accessing CD/DVD/BD with maximum speed

A single front-end SOC with the capability to access all kinds of optical disc is presented. It has the capability to process CD/DVD/BD with maximum speed. It contains an analog front end (AFE), partial response maximum likelihood (PRML) detector, servo-control block, buffer control block etc. It also has numerous analog cores such as analog-to-digital converter (ADC) and phase locked loop (PLL) and digital macros such as digital signal processor (DSP), ARM microprocessor and memories. The presented SOC parallelizes the embedded blocks with the divided channel frequency to enable maximum speed access. It contains 32 million transistors in a 63 mm2 die, and is fabricated with 0.13 mum CMOS technology. It has a channel frequency of 530 MHz and a power consumption of 1.1 W at BD 1x speed. It was fully verified with CD/DVD/BD with maximum speed.

Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

History of the Development of Swiss Watch Microprocessors

While the microprocessors used today in most personal computers, PDA's and self-phones are very well known, the evolution of watch microprocessors is a completely unknown and a very Swiss or Neuchatel story. Christian Piguet, a designer of low-power low-voltage integrated circuits in CMOS technology and the author of more than a dozen patents on digital design, microprocessors and watch systems, provides a first hand view of this chronology.