Digital Control Logic Research Articles

Modified single‐carrier multilevel sinusoidal pulse width modulation for asymmetrical insulated gate bipolar transistor‐clamped grid‐connected inverter

Conventional sinusoidal pulse width modulation (SPWM) for single-phase asymmetrical seven-level insulated gate bipolar transistor (IGBT)-clamped grid-connected inverter (IC-GCI) needs an additional logic operation circuit and a dead zone generation circuit, which raises cost and complicates the implementation. In addition, both added circuitries decrease the reliability. In this study, a modified single-carrier multilevel SPWM (MSCM-SPWM) scheme suitable for IC-GCI is proposed. By setting one carrier, three digital signals to identify voltage zones and six equivalent modulation waves, the control signals of the switches in IC-GCI can be generated with only one digital signal processor controller and simple logic operation. It makes the implementation of the multilevel GCI easier. The detailed spectral character of the MSCM-SPWM is originally derived based on double-Fourier integral theory and then compared with the conventional scheme. It proves that they own the similar spectral character. Detailed simulation and experimental results verify the accuracy and feasibility of the MSCM-SPWM and the single-phase IC-GCI.

A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure**Project supported by the National Basic Research Program of China (No. 2014CB744600) and the National Natural Science Foundation of China (No. 61474120).

As a key building block of data acquisition systems, power dissipation of the successive approximation register (SAR) ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35 μm CMOS technology and has a core die area of 1.12 mm2. A signal-to-noise-and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from −55 to 150 °C. The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage.

A Resistance Deviation-to-Time Interval Converter Based on Dual-Slope Integration Using Second Generation Current Conveyors

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to 15.56 μs/Ω over the resistance deviation range of 0-200 Ω and its linearity error is less than ±0.02%. Its temperature stability is less than 220 ppm/℃ in the temperature range of -25-85℃.

Assessment of multilevel inverter using embedded and digital controller for various loads

This paper presents a new symmetrical multilevel inverter based on seven-level inverter by using non-pwm technique. In embedded controller, codings are written for the generation of pulse. Codings are composed by switching states. Embedded switching scheme is used to meliorate the functioning of the multi level inverter. While in digital controller logic gates and flip flop are used to generate pulses. This proposed topology produces seven-level inverters which are nearer to the sinusoidal wave. The switching scheme reduces the THD, switching loss and increase output level FFT analysis and output result of the inverter with R-load, RL load and induction motor has been analysed by using MATLAB/Simulink.

Controllable high-power, variable-frequency CMOS circuit for microactuator applications

A large-output power, high-current high-voltage, CMOS driving circuit for electrothermal microactuators is presented in this work. The circuit addresses the challenge of providing microelectromechanical systems devices with a monolithic integrated circuit that is capable of outputting high voltage with low output resistance that matches the actuator load for maximum power transfer. The circuit is implemented using a modified eight-stage charge pump. A digital control logic is designed to control the working charge pump stages in order have a variable output voltage between 4 and 15.5 V on a load producing about 150 mW maximum output power. To the authors’ knowledge, the circuit’s output resistance is the lowest among charge pumps that are capable of producing such high voltages. An AC pulse output of 15.5 V amplitude and variable frequency between 60 and 2000 Hz is included in the circuit. The circuit is operated by a conventional 5 V supply. With the variable DC output voltage level and AC output capability, the circuit is suitable for driving many electrothermal microactuators. The total size of the chip excluding pads is 5 mm2.

A Wideband Cmos Phase Shifter With A Phase Tuning Bit for Ku‐Band Mobile Satellite Communication

ABSTRACTThis article presents a Ku‐band switched path type phase shifter in a standard 0.13 µm CMOS technology. The phase shifter consists of phase shifting filter networks, DPDT and SPDT switches, a tuning bit, and digital control logic. The phase coverage of the phase shifter is 354° with the LSB of 5.625°. The measured insertion loss is less than 16 dB. The input and output return losses are more than 12 dB. The RMS phase error and amplitude variation are less than 7.6° and 0.3 dB at 10.7–15 GHz, respectively. When the tuning bit is activated, the RMS phase error of 6.3° and the RMS amplitude variation of 0.4 dB are achieved at 10.7–15 GHz. The input P1dB over ∼11 dBm is achieved at 10–15 GHz. The current consumption is nearly zero with 1.2 V supply voltage. The chip size is 1.46 × 0.82 mm2 including pads. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2120–2124, 2013

디지털 컨트롤러 공유 및 Pseudo Relaxation Oscillating 기법을 이용한 원-칩 다중출력 SMPS

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through independently operating in each dedicated time periods. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple was 11 mV at 3.3V output voltage. Over/undershoot voltage was 10mV/19.6mV at 3.3V output voltage. The noise performance was simulated at 800mA and 100KHz load regulation. Core circuit can be implemented small size in area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD technology.

Array Test Structures for Gate Dielectric Integrity Measurements and Statistics

An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the stress induced degradation of transistor parameters. The test array has been fabricated in a standard mixed-mode 130 nm CMOS technology. As such technologies offer both thin and thick gate dielectrics for MOS transistors, different gate dielectric thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages and prevent the control logic from degradation.

A 630dpi dynamic LED display array in standard Si-based CMOS technology

A novel silicon light emitting diode (LED) display array has been fabricated using 0.35 μm standard CMOS technology. In this array, an LED and static random access memory (SRAM) are integrated together in a special layout. The SRAM in each pixel can store the state of the pixel and ensure that the pixel remains lit without persistent flashing. As a result, the control logic is perfectly integrated on the same wafer. Two power sources are used to drive the display array because the LEDs operate at high voltage (supply voltage of 9 V), and the current of the whole display array is about 30–60 mA to display common characters. The display circuit includes digital control logic circuits and SRAM, and requires a supply voltage of 3.3 V. The area of a single pixel is 40×40 μm2, the area of the whole 16×16 LED array is 1 mm2, and the display density is 630 dpi.

A Four-Antenna 802.11a Receiver integrated in 0.25 µm SiGe BiCMOS with Spatial Weighting

This paper presents the design and results of a four-antenna integrated receiver (RX) frontend in 0.25 µm SiGe BiCMOS. It performs antenna combining in the radio-frequency (RF) domain with IEEE 802.11a compliant signals. Therefore, the RF part of this integrated circuit (IC) includes four low noise amplifiers (LNAs), vector modulators (VMs) and a signal combiner. These circuits can weight the incoming C-band (5.6 GHz) signals in their I- and Q-components with an 8-bit resolution before superposition and downcoversion. The baseband (BB) part of the applied zero-IF architecture integrates an 8th order switched-capacitor (SC) filter for channel selection and variable gain amplifiers (VGAs) for automatic gain control (AGC). Together with digital control logic the power consumption amounts to 350 mW at an area requirement of 7.5 mm2.

GOSSIPO-3: measurements on the prototype of a read-out pixel chip for Micro-Pattern Gaseous Detectors

GOSSIPO-3 is a demonstrator of a front-end chip designed in IBM 130 nm CMOS in collaboration between Nikhef (Amsterdam) and the Physics Department of the University of Bonn for the read-out of Micro-Pattern Gas Detectors.The prototype features charge sensitive amplifiers, discriminators, a high resolution Time to Digital Converter (TDC), two different Low Drop Out (LDO) voltage regulators for supply voltage control of the Time to Digital Converter, biasing circuits and control logic on a 2 × 1 mm2 die. The chip can be operated in a time measuring mode or an event counting mode. Following the prototype announcement at the TWEPP 2009, measurement data on gain, noise performance, channel to channel ToT spread and LDO load step responses is now available. The measurement results confirm the high gain and low noise (ENC = 25 e−) predicted by simulations. Stable and reproducible time bin sizes of the TDC are also confirmed.

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> ) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

Static control logic for microfluidic devices using pressure-gain valves

A microfluidic valve that amplifies the pressure in a fluid channel enables the realization of static microfluidic digital control logic. This in turn could enable more versatility and integration in the control of flows in ‘lab-on-a-chip’ systems.

Rancang Bangun Tacho Generator Sebagai Sensor Kecepatan Pada Praktikum Kendali Motor-Motor Listrik

The research implementing “Tachogenerator as the sensor for controller of Electric Motor Speed rotation at electric laboratories” Plant (Object controlled) is controlled by the electric motors speed rotation in AC or DC, by setting armature voltage of motor using digital PID controller and fuzzy logic from Personal Computer (PC). Although the load disturbances are changing significantly, but the motor speed rotation can be stabilized by feedback input from tachogenerator which are the focus in this research. PID controller dan fuzzy Logic controller applications are used to find the advantages the disadvatages or controll methode of motor reliability in dinamic controll (speed rotation) which cause the system more stabil. The result can be seen in maintained system responses and the system reliabilty against disturbances.

Identification, digital control and fuzzy logic techniques applied to a synchronous generator

The experimental results obtained in the design and implementation of an decoupled digital speed and voltage controller for a micro-energy system are reported in this work. The studied system is formed by a 9Kw DC motor driving a 10KVA synchronous machine. There are two control loops in the proposed controller: the speed control (Speed Governor) and the control of the stator's voltage (Automatic Voltage Regulator). Each control loop was designed using linear control techniques and Fuzzy control techniques. Tests on the system show the performance of the proposed controllers.

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the "Dose Control Circuitry" (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 ?m CMOS process.

Digital power-factor correction for a capacitor-charging power supply

The design and construction of a low-power low-cost power supply capable of charging an energy storage capacitor from a 120-V AC source and capable of power-factor correction (PFC) is presented. The load that is generally connected to a capacitor-charging power supply (CCPS) is a pulsed power load (i.e., laser, cardiac defibrillator, or flash lamp). A flyback converter was incorporated into the CCPS because it is capable of charging a capacitor while maintaining a high power factor. The control system of the CCPS uses peak current control to achieve PFC and is implemented using standard off-the-shelf digital logic components. A 300-V prototype has been constructed and tested. The experimental results show that a high power factor is obtained by the CCPS utilizing a flyback converter and the digital logic control system.

A test system for calibrating flickermeters

This paper describes a new calibration system for testing flickermeters. The test system is used to generate and measure all the combinations of amplitude changes and frequencies required for calibrating flickermeters. Two computer-controlled waveform generators are used to produce the test conditions. The percent modulations of the test waveforms are measured with two high accuracy sampling voltmeters. Digital logic and software control ensures that the modulated signals are only measured when either maximum or minimum modulation occurs. Test data indicates that the percent modulation of the waveforms generated by the calibration system for square wave and sinusoidal modulations are within 0.002% and 0.005%, respectively, of the nominal values specified in IEC Standard 61000-3-3.

Active vibration control of a suspension system using an electromagnetic damper

This paper is concerned with the design and implementation of a magnetic damper system to reduce the vibration of a suspension system actively. A cylindrical-type electromagnetic actuator with a permanent magnet is analysed and an effective controller design is made. An accurate force analysis is carried out for the given system. An accurate transfer function for the total system is determined by experimental data using an error minimization method. For experiments, a simple suspension structure system is utilized, in which a magnetic damper composed of a permanent magnet and digital controller is attached. In order to drive the system, a bipolar power amplifier of the voltage control type is utilized. A stable and high speed control board is used to implement digital control logic for the given system. This paper shows that the magnetic damper system using a phase lead controller is excellent in reducing the vibration of a one-degree-of-freedom suspension system.

Controlling of overfilling in food processing

World-wide interest in the environment has promoted significant commercial attention to the elimination and disposal of waste products and hazardous materials. In addition, despite less publicity in the media, there has been a growing research base in the elimination of waste resulting from inefficient production processing. In food processing, considerable waste produce arises in the form of `giveaways', in overfilled containers, or through `throwaways' as non-conforming underfilled products which end up in rubbish bins. The major aim of the current research programme is to investigate the use of ultrasound monitoring, as a means of on-line measurement of fluid levels in food containers. Ultrasound monitoring has the potential to be an accurate measurement technique which is capable of being combined with an appropriate control strategy to provide the most suitable method of reducing or eliminating the waste problem. The objective of the research described herein was to investigate controller design methodologies for a bottling process. The bottling process was modelled using MATLAB ® and SIMULINK ® packages and controller designs were implemented to improve the response characteristics of the process. Both digital control and fuzzy logic controller design methods were investigated. The digital controller was designed using the direct digital design method and resulted in an improved system performance. However, when different carousel delays were considered, the performance varied significantly. Fuzzy logic control operates with a pre-determined set of rules and has been shown to function very well with a bottling system. Bottle fill times and the resulting stability with respect to changing carousel delays were improved. Available data indicates that fuzzy logic can be used efficiently and effectively, which could provide a valuable asset to the food processing and allied industries.